High availability error self-recovering shared cache for multiprocessor systems

• US 6,014,756 A
• Filed: 12/16/1996
• Issued: 01/11/2000
• Est. Priority Date: 04/18/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leppla, Bernd, Udo, Wille, Dottling, Gerhard, Getzlaff, Klaus-Jorg
• Primary Examiner(s): WRIGHT, NORMAN M
• Application Number:
  US08/765,010
• Time in Patent Office: 1,121 Days
• Field of Search: 395/182.13, 395/182.04, 395/185.01, 711/141, 711/147, 711/118, 711/101, 711/130, 711/131, 711/149, 711/142, 711/150, 714/15, 714/6, 714/48
• US Class Current: 714/15
• CPC Class Codes: G06F 11/141 for bus or memory accesses

Abstract

A high availability shared cache memory in a tightly coupled multiprocessor system provides an error self-recovery mechanism for errors in the associated cache directory or the shared cache itself. After an error in a congruence class of the cache is indicated by an error status register, self-recovery is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting Valid bits to "0" and by setting the Parity bit to a correct value, wherein the request for data to the main memory is not cancelled.

Multiple bit failures in the cached data are recovered by setting the Valid bit in the matching column to "0". The processor reissues the request for data, which is loaded into the processor'"'"'s private cache and the shared cache as well. Further requests to this data by other processors are served by the shared cache.

Claims

1. A high availability shared cache in a multiprocessor system having at least two processing units, for storing information as congruence classes to be utilized by the processing units, wherein the multiprocessor system comprises:

cache means associated with each of said processing units for storing information to be utilized by the processing units;

main memory means for storing information to be utilized by the processing units, which are managed by arbitration means;

bus means for transferring information between the processing units, the shared cache, and the main memory means;

shared cache directory means for managing the shared cache, comprising entries of all the information stored in the shared cache, a Valid bit for the status of the information stored in the shared cache, and a Parity bit for indicating errors in the shared cache; and

error status register means for recording error events, which are provided by the shared cache;

wherein a request for information is transmitted to the shared cache and the main memory means, in parallel, and in case of the error status register means recording an error in any entry of a congruence class in the shared cache directory means, self-recovery of the shared cache is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting the Valid bits to "0" and by setting the Parity bit to a correct value; and

the request for information to the main memory means is not cancelled.

2. The shared cache according to claim 1, wherein the cache means associated with each processing unit provide a Valid bit, a Multiple Copy bit and a Change bit, and the shared cache directory means further provides a Multiple Copy bit, for the status of the information stored therein.

3. The shared cache according to claim 1, wherein information provided by the main memory means is loaded into the shared cache and the cache means, which are associated with the processing units, in parallel.

4. The shared cache according to claim 3, wherein after the requested information is received by the requesting processing unit and the shared cache, both validate the corresponding entry in their cache directories by setting the Valid bits to "1".

5. The shared cache according to claim 1, wherein if for more than one congruence class an error is indicated, the corresponding Valid bits in the shared cache directory means are set to "0".

6. The shared cache according to claim 1, wherein in case of a frequently found erroneous entry, the corresponding entry of the shared cache directory means is cancelled by setting a Delete bit.

11. A multiprocessor computer system comprising a high availability shared cache memory with an error self-recovery mechanism according to claim 1.

7. A high availability shared cache in a multiprocessor system having at least two processing units, for storing information, to be utilized by the processing units, as congruence classes, wherein the multiprocessor system comprises:

cache means associated with each of said processing units for storing information to be utilized by the processing units;

main memory means for storing information to be utilized by the processing units, which are managed by arbitration means;

bus means for transferring information between the processing units, the shared cache, and the main memory means;

shared cache directory means for managing the shared cache, comprising entries of all the information stored in the shared cache, a Valid bit for the status of the information stored in the shared cache, and a Parity bit for indicating errors in the shared cache; and

error status register means for recording error events, which are provided by the shared cache;

wherein a request for information is transmitted to the shared cache and the main memory means, in parallel, and in case of multiple bit failures in the shared cache as indicated by an error correction facility, self-recovery of the shared cache is accomplished by invalidating matching entries in the shared cache directory means of the corresponding congruence class by resetting the Valid bits to "0" and by informing the requesting processing unit that the information can not be provided, whereby the processing unit issues the request for information again and the request is served by the main memory means.

8. The shared cache according to claim 7, wherein the cache means associated with each processing unit provide a Valid bit, a Multiple Copy bit and a Change bit, and the shared cache directory means further provides a Multiple Copy bit, for the status of the information stored therein.

9. The shared cache according to claim 7, wherein information provided by the main memory means is loaded into the shared cache and the cache means, which are associated with the processing units, in parallel.

10. The shared cache according to claim 7, wherein after the requested information is received by the requesting unit and the shared cache, both validate the corresponding entry in their cache directories by setting the Valid bits to "1".

12. A multiprocessor computer system comprising a high availability shared cache memory with an error self-recovery mechanism according to claim 7.