At-speed scan testing
First Claim
1. A method of scanning an integrated circuit, comprising the steps of:
- transmitting a scan input in parallel from a tester to the integrated circuit;
converting the scan input at the integrated circuit from parallel to serial; and
passing the serialized scan input through scan circuitry of the integrated circuit, to create a serial scan output.
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Accused Products
Abstract
A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
85 Citations
27 Claims
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1. A method of scanning an integrated circuit, comprising the steps of:
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transmitting a scan input in parallel from a tester to the integrated circuit; converting the scan input at the integrated circuit from parallel to serial; and passing the serialized scan input through scan circuitry of the integrated circuit, to create a serial scan output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit comprising:
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a plurality of data storage elements having inputs and outputs; a plurality of logic functions having inputs, and outputs connected to respective inputs of said data storage elements; a scan path; and means for scanning said data storage elements using said scan path at a normal operating speed of the integrated circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A scan system comprising:
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an integrated circuit; a tester; and means connecting said integrated circuit to said tester such that said tester can perform a scan of said integrated circuit at an effective speed which is equal to a normal operating speed of said integrated circuit. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification