Vertical field effect transistor and manufacturing method thereof

• US 6,015,725 A
• Filed: 08/19/1997
• Issued: 01/18/2000
• Est. Priority Date: 08/22/1996
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hirayama, Teruo
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): SULSKY, MARTIN S
• Application Number:
  US08/914,096
• Time in Patent Office: 882 Days
• Field of Search: 438/138, 438/156, 438/192, 438/268, 438/270
• US Class Current: 438/156
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).

Claims

1. A method of manufacturing a vertical field effect transistor, comprising in the following order the steps of:

forming separate buried layers of a second conduction type by ion implantation to a predetermined depth in a semiconductor substrate of a first conduction type;

forming a recess for each buried layer, each recess having a width smaller than the width of said buried layer and having the bottom thereof located within said buried layer of said semiconductor substrate and with adjacent recesses being separated by a protrusion;

forming a gate insulation film on the side walls of the protrusion;

forming a gate electrode on the gate insulating film on the side wall of the protrusion;

forming an impurity region making up a source and a drain on the surface of said protrusion and on the bottom surface of said recess;

providing an insulating layer to cover the protrusions and fill the recesses;

forming an opening in the insulating layer above each protrusion; and

forming a plug contact in the opening contacting the upper surface of each protrusion.

2. A method of manufacturing a vertical field effect transistor according to claim 1, wherein said buried layer is thermally diffused after ion implantation.

3. A method according to claim 1, wherein the step of forming separate buried layers includes forming an insulating film layer on the semiconductor material before ion implantation and then forming a first mask on the insulating film layer for the ion implantation, and wherein the step of forming a recess includes etching portions of the insulating film layer using the first mask to form remaining portions, then removing the first mask, covering the remaining portions of the insulating film layer with an insulating oxide film, etching the insulating oxide film to form side wall films on the remaining portions and then using the remaining portions with the side wall films as a second mask when forming the recesses.