×

Vertical field effect transistor and manufacturing method thereof

  • US 6,015,725 A
  • Filed: 08/19/1997
  • Issued: 01/18/2000
  • Est. Priority Date: 08/22/1996
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of manufacturing a vertical field effect transistor, comprising in the following order the steps of:

  • forming separate buried layers of a second conduction type by ion implantation to a predetermined depth in a semiconductor substrate of a first conduction type;

    forming a recess for each buried layer, each recess having a width smaller than the width of said buried layer and having the bottom thereof located within said buried layer of said semiconductor substrate and with adjacent recesses being separated by a protrusion;

    forming a gate insulation film on the side walls of the protrusion;

    forming a gate electrode on the gate insulating film on the side wall of the protrusion;

    forming an impurity region making up a source and a drain on the surface of said protrusion and on the bottom surface of said recess;

    providing an insulating layer to cover the protrusions and fill the recesses;

    forming an opening in the insulating layer above each protrusion; and

    forming a plug contact in the opening contacting the upper surface of each protrusion.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×