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Damascene formation of borderless contact MOS transistors

  • US 6,015,727 A
  • Filed: 06/08/1998
  • Issued: 01/18/2000
  • Est. Priority Date: 06/08/1998
  • Status: Expired due to Fees
First Claim
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1. A method of making a semiconductor device comprising:

  • providing a substrate;

    forming a first dielectric layer over said substrate;

    etching one or more openings in said first dielectric layer, wherein said openings define the location of MOS transistors;

    depositing a material layer over said substrate to fill said openings;

    pattering said material layer to define source and drain regions adjacent to a remaining portion of said material layer;

    doping said source and drain regions with dopants;

    depositing a second dielectric layer over said source and drain regions;

    removing said remaining portion of said material layer to define a channel region in said substrate said channel region disposed between said source and drain regions;

    depositing a third dielectric layer over said channel region to form a gate insulating layer;

    etching contact openings over said source and drain regions;

    forming contacts over said gate insulating layer and in said contact openings.

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