Damascene formation of borderless contact MOS transistors

• US 6,015,727 A
• Filed: 06/08/1998
• Issued: 01/18/2000
• Est. Priority Date: 06/08/1998
• Status: Expired due to Fees

• Current Assignee: Frank M. Wanlass
• Original Assignee: Frank M. Wanlass
• Inventors: Wanlass, Frank M.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US09/093,221
• Time in Patent Office: 589 Days
• Field of Search: 438/275, 438/300, 438/528, 438/595, 438/585, 438/301, 438/303, 438/218, 438/221, 438/229, 438/294
• US Class Current: 438/218
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention is a processing method for forming MOS transistors. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to MOS gate electrodes directly over channel regions, and allows borderless connections to be made to source and drain regions, thereby improving layout density of small transistors. The method enables interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon. The method also prevents plasma damage of very thin gate dielectrics during processing.

Claims

1. A method of making a semiconductor device comprising:

providing a substrate;

forming a first dielectric layer over said substrate;

etching one or more openings in said first dielectric layer, wherein said openings define the location of MOS transistors;

depositing a material layer over said substrate to fill said openings;

pattering said material layer to define source and drain regions adjacent to a remaining portion of said material layer;

doping said source and drain regions with dopants;

depositing a second dielectric layer over said source and drain regions;

removing said remaining portion of said material layer to define a channel region in said substrate said channel region disposed between said source and drain regions;

depositing a third dielectric layer over said channel region to form a gate insulating layer;

etching contact openings over said source and drain regions;

forming contacts over said gate insulating layer and in said contact openings.

2. The method of claim 1, wherein said first dielectric layer includes an etch stop layer;

and

wherein said material layer is pattered by anisotropic etching stopping before etching through said etch stop layer.

3. The method of claim 1, wherein said step of depositing said material layer further includes polishing said material layer so that said material layer remains in only said openings and wherein said material layer is substantially coplanar with said first dielectric layer.

4. The method of claim 1, wherein said first dielectric layer has a characteristic etch rate different than that of said material layer and different than that of said second dielectric layer.

5. The method of claim 1, wherein said second dielectric layer over said source and drain region is polished to be substantially coplanar with said first dielectric layer.

6. The method of claims 3 and 5, wherein said polishing is chemical mechanical polishing.

7. The method of claim 1, wherein forming said contacts further includes the steps of:

depositing a conductive layer over said substrate before the step of etching contact openings over said source and drain regions;

depositing a conducting material over said conductive layer and in said contact openings wherein said conducting material forms electrical contact with said substrate and wherein said conducting material acts as a barrier layer;

depositing an electrical contact material over said substrate and filling said contact openings; and

patterning and isolating a conductor over said electrical conduct material to make electrical contact with said source and drain regions and said conducting material over said channel region.

8. The method of claim 1, further includes doping said channel region to control punch through, threshold voltage and field inversion.

9. The method of claim 1, wherein the step of doping said source and drain region includes controlling junction profiles to minimize hot carrier effects.

10. The method of claim 2, wherein said first dielectric material is a silicon nitride, and wherein said etch stop layer is a silicon oxide, and wherein said second dielectric material is a silicon oxide and wherein said gate insulating layer is a silicon oxide.

11. The method of claim 7, wherein said conducting layer is TiN, and wherein said conducting material is a multilayer comprising a first layer of Ti and a second layer of TiN, and wherein said contact material is tungsten, and wherein said conductor is aluminum.

12. The method of claim 1, wherein said material layer is selected from the group consisting of amorphous silicon or polysilicon.

13. A method for making a semiconductor device comprising:

providing a substrate;

forming a first dielectric layer over said substrate;

forming a second dielectric layer over said substrate;

etching one or more openings in said second dielectric layer wherein said openings define the location of MOS transistors;

depositing a material layer over said substrate to fill said openings;

removing said material layer except in said openings,

patterning said material layer to define source and drain regions;

implanting dopants through said first dielectric layer into said substrate to form source and drain regions;

depositing a third dielectric layer in said openings, said third dielectric layer disposed above said source and drain regions;

removing said pattered material layer;

removing said first dielectric layer from a region disposed between said source and drain regions to define a channel region in said substrate;

depositing a fourth dielectric layer over said channel region to form a gate insulting layer;

activating and diffusing said dopants;

depositing a first layer of TiN over said substrate;

etching contact openings over said source and drain regions;

depositing a layer of Ti over said substrate;

depositing a second layer of TiN over said substrate;

depositing a layer of tungsten over said contact openings and over said channel region; and

patterning and isolating a conductive material over said insulating layer and said source and drain regions.

14. The method of claim 13, wherein said first dielectric layer is a silicon oxide layer which acts as an etch stop during the step of patterning said material layer to define said source and drain regions so that said first dielectric layer remains over said source and drain regions.

15. The method of claim 13, wherein said step of depositing said material layer further includes polishing said material layer so that said material layer only remains in said openings and wherein said material layer is substantially coplanar with said second dielectric layer.

16. The method of claim 13, wherein said third dielectric layer over said source and drain region is polished to be substantially coplanar with said second dielectric layer.

17. The method of claims 15 and 16, wherein said polishing is chemical mechanical polishing.

18. The method of claim 13, further includes doping said channel region to control punch through, threshold voltage and field inversion.

19. The method of claim 13, wherein the step of doping said source and drain region includes controlling junction profiles to minimize hot carrier effects.

20. The method of claim 13, wherein said material layer is selected from the group consisting of amorphous silicon or polysilicon.