Method for fabricating transistorless, multistable current-mode memory cells and memory arrays

• US 6,015,738 A
• Filed: 11/17/1997
• Issued: 01/18/2000
• Est. Priority Date: 05/05/1994
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Levy, Harold J., McGill, Thomas C.
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US08/972,118
• Time in Patent Office: 792 Days
• Field of Search: 257/910, 438/275, 438/238, 438/237, 438/979, 438/257-258
• US Class Current: 438/275
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2211/5614 Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: Y10S 438/979 Tunnel diodes

Abstract

A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind.

Claims

1. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprising the steps of:

forming a first conducting layer;

forming a first semiconductor layer coupled to the first conducting layer;

forming a second semiconductor layer coupled to the first semiconductor layer;

patterning the second semiconductor layer;

etching the second semiconductor layer, the first semiconductor layer and the first conducting layer;

forming a second conducting layer coupled to the second semiconductor layer;

patterning and etching the second conducting layer;

etching the second semiconductor layer using the second conducting layer as a mask to form a plurality of semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form a plurality of semiconducting devices of a first kind.

2. The method as defined by claim 1 wherein the semiconducting devices of the first kind are either of switch diodes or load devices.

3. The method as defined by claim 2 wherein the semiconducting devices of the second kind are either of load devices or switch diodes,

wherein the semiconducting devices of the first kind and the semiconducting devices of the second kind are different so that

when the semiconducting devices of the first kind are the switch diodes, the semiconducting devices of the second kind are the load devices, and

when the semiconducting devices of the first kind are the load devices, the semiconducting devices of the second kind are the switch diodes.

4. The method as defined by claim 3 wherein each of the memory cells includes one of the load devices and one of the switch diodes.

5. The method as defined by claim 4 wherein the first conducting layer comprises either of bit lines or word lines, and the second conducting layer comprises either of word lines or bit lines

wherein the first conducting layer and the second conducting layer are different so that

when the first conducting layer includes the word lines, the second conducting layer includes the bit lines, and

when the first conducting layer includes the bit lines, the second conducting layer includes the word lines.

6. The method as defined by claim 5 wherein each of the load devices is connected to a corresponding one of either of the word lines or bit lines, and each of the switch diodes is connected to a corresponding one of either of the bit lines or the word lines.

7. The method as defined by claim 3 wherein the switch diodes exhibit negative differential resistance, and the load devices exhibit one of an exponential current-voltage characteristic and a linear current-voltage characteristic.

8. The method as defined by claim 3 wherein

each of the switch diodes comprises one of a first homojunction device, a first heterojunction device and a first Schottky diode,

the first homojunction device comprising at least one P-type semiconducting region of a semiconductor and at least one N-type semiconducting region of the same semiconductor,

the first heterojunction device comprising at least one P-type semiconducting region of a semiconductor and at least one N-type semiconducting region of another semiconductor,

the first Schottky diode comprising a semiconductor and a metal region;

each of the load diodes exhibiting the exponential current-voltage characteristic comprises one of a second homojunction device, a second heterojunction device and a second Schottky diode,

the second homojunction device comprising at least one P-type semiconducting region of a semiconductor and at least one N-type semiconducting region of the same semiconductor,

the second heterojunction device comprising at least one P-type semiconducting region of a semiconductor and at least one N-type semiconducting region of another semiconductor,

the second Schottky diode comprising a semiconductor and a metal region; and

each of the load diodes exhibiting the linear current-voltage characteristic comprises one of a P-type semiconducting region, an N-type semiconducting region and a metal region.

9. The method as defined by claim 8 wherein the switch diodes exhibit N-type negative differential resistance including a high-impedance region, a low-impedance region and a negative-resistance region.

10. The method as defined by claim 1 wherein patterning the second semiconductor layer and patterning the second conducting layer incorporate a lithographic process, and

wherein the lithographic process includes coating a layer of photoresist and exposing the layer of photoresist using one of optical, electron beam, ion beam and X-ray lithography.

11. The method as defined by claim 1 wherein the step of etching the second semiconductor layer, the first semiconductor layer and the first conducting layer followed by patterning of the second semiconductor layer is accomplished sequentially using different etching methods to selectively etch one layer and not the other layers to minimize undercutting wherein an etching method is one of a wet etch and a dry etch.

12. The method as defined by claim 1 wherein the step of etching the second semiconductor layer, the first semiconductor layer and the first conducting layer followed by patterning of the second semiconductor layer is accomplished simultaneously using one etching method.

13. The method as defined by claim 1 wherein the step of forming a second conducting layer includes planarizing the second semiconductor layer.

14. The method as defined by claim 13 wherein the step of planarizing the second semiconductor layer includes filling hollow regions by spin coating photoresist wherein the hollow regions are formed when materials of the second semiconductor layer, the first semiconductor layer and the first conducting layer are removed.

15. The method as defined by claim 13 wherein the step of planarizing the second semiconductor layer includes depositing an insulating material as a gap filler and etching back the insulating material so that the second semiconductor layer is planar with the gap filler.

16. The method as defined by claim 1 wherein the step of etching the second semiconductor layer and the first semiconductor layer using the second conducting layer as a mask is accomplished sequentially using different etching methods to selectively etch one layer and not the other layer to minimize undercutting wherein an etching method is one of a wet etch and a dry etch.

17. The method as defined by claim 1 wherein the step of etching the second semiconductor layer and the first semiconductor layer using the second conducting layer as a mask is accomplished simultaneously using one etching method.

18. The method as defined by claim 1 wherein etching the second semiconductor layer followed by patterning the second semiconductor layer forms second semiconducting strips;

etching the first semiconductor layer followed by patterning the second semiconductor layer forms first semiconducting strips;

etching the first conducting layer followed by patterning the second semiconductor layer forms first conducting strips;

patterning and etching the second conducting layer forms second conducting strips;

etching the second semiconductor layer using the second conducting layer as a mask forms second semiconducting islands; and

etching the first semiconductor layer using the second conducting layer and the second semiconductor layer as a mask forms first semiconducting islands.

19. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprising the steps of:

forming a first conducting layer;

forming a first semiconductor layer over the first conducting layer;

forming a second semiconductor layer over the first semiconductor layer;

patterning the second semiconduct or layer ;

etching the second semiconductor layer, the first semiconductor layer and the first conducting layer;

forming a second conducting layer over the second semiconductor layer;

patterning and etching the second conducting layer;

etching the second semiconductor layer using the second conducting layer as a mask to form a plurality of semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form a plurality of semiconducting devices of a first kind.