Method of metal/polysilicon gate formation in a field effect transistor

• US 6,015,747 A
• Filed: 12/07/1998
• Issued: 01/18/2000
• Est. Priority Date: 12/07/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pramanik, Shekhar, Nogami, Takeshi, Lopatin, Sergey
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/206,799
• Time in Patent Office: 407 Days
• Field of Search: 438/586, 438/592, 438/678, 427/98, 427/304, 427/305
• US Class Current: 438/586
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for manufacturing a field effect transistor (100) includes forming source and drain regions (110, 112) in a semiconductor substrate (102) and forming a polysilicon gate (104) on a surface (106) of the semiconductor substrate adjacent to the source and drain regions. A masking layer (136) is formed, covering substantially all the semiconductor substrate. Portions of the masking layer are then selectively removed to expose at least selected portions of the polysilicon gate. Selected portions of the polysilicon gate are partially etched. By selective electroless metal deposition, a metal layer (146) is formed on the etched selected portions of the polysilicon gate. In an alternative embodiment, the masking layer is removed before selective deposition of the electroless metal, so that electroless metal is simultaneously deposited on the polysilicon gate and the source region and the drain region.

Claims

1. A method for manufacturing a field effect transistor, the method comprising the steps of:

forming source and drain regions in a semiconductor substrate;

depositing polysilicon on a surface of the semiconductor substrate between the source and drain regions;

forming first and second oxide spacers adjacent the polysilicon on the surface of the semiconductor substrate;

forming a masking layer covering substantially all the semiconductor substrate;

selectively removing portions of the masking layer to expose at least selected portions of the polysilicon;

removing a part of the selected portions of the polysilicon to an etch depth to define a trench between the first and second oxide spacers, the trench exposing a deposition surface of the polysilicon for forming the metallpolysilicon layer; and

selectively depositing electroless metal to form a metal/polysilicon gate in the trench at the selected portions of the polysilicon.

2. A method for manufacturing a field effect transistor as recited in claim 1 wherein selectively removing portions of the masking layer comprises removing only a portion of the masking layer over the polysilicon.

3. A method for manufacturing a field effect transistor as recited in claim 2 wherein selectively removing portions of the masking layer filler comprises removing portions of the masking layer covering the source and drain regions and wherein the method further comprises the step of selective deposition of electroless metal on the source and drain regions.

4. A method for manufacturing a field effect transistor as recited in claim 1 wherein the electroless metal comprises a metal selected from the group consisting of nickel, cobalt, nickel phosphide, cobalt phosphide, nickel tungsten phosphide and copper tungsten phosphide.

5. A method for manufacturing a field effect transistor as recited in claim 1 wherein the method further comprises the step of:

after exposing the deposition surface of the polysilicon, exposing source/drain deposition surfaces of the source and drain regions; and

selectively depositing electroless metal on the source and drain regions as well as the selected portions of the polysilicon.

6. A method for manufacturing a field effect transistor as recited in claim 5 wherein the electroless metal comprises a metal selected from the group consisting of nickel, cobalt, nickel phosphide, cobalt phosphide, nickel tungsten phosphide and cobalt tungsten phosphide.

7. A method for manufacturing a field effect transistor, the method comprising the steps of:

forming a polysilicon gate on a surface of a semiconductor substrate, the polysilicon gate having a predetermined thickness;

forming a source region in the semiconductor substrate on a first side of the polysilicon gate and forming a drain region in the semiconductor substrate on a second side of the polysilicon gate;

forming a first spacer immediately adjacent the first side of the polysilicon gate and a second spacer immediately adjacent the second side of the polysilicon gate, the first spacer and the second spacer extending from the surface of the semiconductor substrate to substantially a top surface of the polysilicon gate;

exposing a deposition surface, including removing a part of the polysilicon gate between the first spacer and the second spacer from the top surface of the polysilicon gate to an etch depth, the etch depth being less than the predetermined thickness of the polysilicon gate, the first spacer, the second spacer and the deposition surface of the polysilicon gate defining a trench; and

filling the trench by selectively depositing electroless metal in the trench to form a metal/polysilicon gate.

8. The method as defined in claim 7 further comprising the steps of forming a masking layer on the surface of the semiconductor substrate except the top surface of the polysilicon gate.

9. The method as defined in claim 8 further comprising the step of, after selectively depositing the electroless metal, removing the masking layer.

10. The method as defined in claim 8 further comprising the steps of:

before selectively depositing the electroless metal, removing the masking layer and exposing the source region and the drain region; and

selectively depositing electroless metal on the source region and the drain region to form ohmic contacts.

11. The method as defined in claim 8 further comprising the step of selecting the electroless metal from the group consisting of nickel, cobalt, nickel phosphide, nickel tungsten phosphide, cobalt phosphide, and cobalt tungsten phosphide.

12. The method as defined in claim 8 further comprising the step of, before selectively depositing the electroless metal, treating the deposition surface with an activating catalyst.

13. The method as defined in claim 8 further comprising the step of selecting the activating catalyst from the group consisting of palladium, silver and gold.