Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits

• US 6,015,992 A
• Filed: 12/30/1997
• Issued: 01/18/2000
• Est. Priority Date: 01/03/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Amerasekera, Ekanayake, Chatterjee, Amitava
• Primary Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US09/001,058
• Time in Patent Office: 749 Days
• Field of Search: 257/350, 257/351, 257/355, 257/358-359, 257/360, 257/361, 257/109, 257/111, 257/154, 257/173
• US Class Current: 257/350
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A bistable SCR-like switch (41) protects a signal line (65) of an SOI integrated circuit (40) against damage from ESD events. The bistable SCR-like switch (41) is provided by a first and a second transistors (42 and 44) which are formed upon the insulator layer (46) of the SOI circuit (40) and are separated from one another by an insulating region (60). Interconnections (62 and 64) extend between the two transistors (42 and 44) to connect a P region (62) of a first transistor (42) to a P region (54) of the second transistor (44) and an N region (50) of the first transistor (42) to an N region (58) of the second transistor (44). The transistors (42 and 44) may be either bipolar transistors or enhancement type MOSFET transistors. For bipolar transistors, the base of an NPN transistor (42) is connected to the collector of a PNP transistor (44) and the base of the PNP transistor (44) is connected to the collector of the NPN transistor (42). MOSFET transistors are similarity connected, with the intermediate portion of the P-well (43) forming channel region of the N-channel transistor (42) connected to the drain of the P-channel transistor (44), and the N-well (45) forming the channel region of the P-channel transistor (44) connected to the drain of the N-channel transistor (42). Resistors (72 and 74) can be connected between the two transistors (42 and 44) to determine the trigger and holding voltages for the bistable SCR-like switch (41).

Claims

1. An ESD protection device for protecting an active circuit fabricated in an SOI integrated circuit, which active circuit is connected to an ESD susceptible terminal, comprising:

a first region of a first conductivity type;

a second region of a second conductivity type opposite to said first conductivity type;

an isolation structure for electrically isolating said first and second regions;

a first bipolar transistor formed in said first region with a base of said first conductivity type;

a second bipolar transistor formed in said second region with a base of said second conductivity type;

a first contact of the first conductivity type material formed in said first region to allow the base of said first bipolar transistor to be connected external to said first region;

a second contact region of the second conductivity type formed in said second region to allow the base of said second bipolar transistor to be connected external to said second region; and

an interconnect structure external to said first and second regions for interconnecting said first and second bipolar transistors to external resistors in an SCR-like configuration.

2. The ESD protection device of claim 1, wherein:

said first bipolar transistor is formed by forming an MOS transistor in said first region with first source/drain regions formed of the second conductivity type material and the channel region thereof comprised of the first conductivity type material, which said first source/drain regions form the collector and the emitter of said first bipolar transistor with the channel region thereof forming the base thereof; and

said second bipolar transistor is formed by forming an MOS transistor in said second region with second source/drain regions formed of the first conductivity type material and the channel region thereof comprised of the second conductivity type material, wherein said second source/drain regions comprise the collector and the emitter of said second bipolar transistor.

3. The ESD protection device according to claim 2, wherein said isolation structure completely isolates said first and second regions.

4. The ESD protection device according to claim 3, wherein said first and second source/drain regions extend vertically downward from the surface of the respective one of said first and second regions to said isolation structure.

5. The ESD protection device according to claim 4, wherein at least one of each of said first and second source/drain regions does not extend the entire length of the respective one of said first and second regions to allow conduction between the respective one of said first and second contacts and respective portions of said first and second regions defining said bases of respective ones of said first and second bipolar transistors which are disposed between respective ones of said first and second source/drain regions.

6. A bistable switch for ESD protection of an SOI integrated circuit having an insulator layer, comprising:

a first transistor having a first P-type region connected to an anode, a second P-type region, and an intermediate N-type region disposed between and adjoining said first and second P-type regions,

a second transistor which is separately disposed from said first transistor with an electrical isolation region therebetween, and having a first N-type region connected to a cathode, a second N-type region, and an intermediate P-type region disposed between and adjoining said first and second N-type regions;

wherein said intermediate P-type region is separately disposed and electrically isolated from said first and second P-type regions by said isolation region and the insulator layer of the SOI integrated circuit, and said intermediate N-type region is separately disposed and electrically isolated from said first and second N-type regions by said isolation region and the insulator layer of the SOI integrated circuit;

a first interconnection electrically connecting said anode to a protected circuit of said SOI integrated circuit;

a second interconnection electrically connecting said intermediate N-type region to said second N-type region;

a third interconnection electrically connecting said intermediate P-type region to said second P-type region;

a fourth interconnection electrically connecting said cathode to a region of the SOI integrated circuit for shunting ESD current passing through the bistable switch; and

an external interconnect structure for interconnecting said first and second transistors to external resistors in an SCR-like configuration.

7. The bistable switch according to claim 6, wherein said first transistor is disposed within a P-well which is disposed upon an insulator of the SOI integrated circuit and said second transistor is disposed within an N-well disposed upon the insulator of the SOI integrated circuit.

8. The bistable switch according to claim 6, wherein:

said first transistor is disposed within an N-well which is disposed upon the insulator layer of the SOI integrated circuit and said second transistor is disposed within a P-well disposed upon the insulator layer of the SOI integrated circuit; and

said N-well forms said intermediate N-type region and said P-well forms said intermediate P-type region, with said N-well and said P-well completely isolated by said isolation region and said insulator layer.

9. An SOI circuit, comprising:

an insulator layer extending within the SOI circuit and having an insulator surface;

a P-well disposed upon said insulator surface;

a N-well disposed upon said insulator surface, spaced apart from said P-well;

an electrical isolation region extending between said P-well and said N-well, and downward to said insulator surface;

first and second N-type regions disposed within said P-well, with said first N-type region spaced apart from said second N-type region by an intermediate region of said P-well;

first and second P-type regions disposed within said N-well, with said first P-type region spaced apart from said second P-type region by an intermediate region of said P-well;

a first interconnection electrically connecting said first P-type region to a protected circuit of the SOI integrated circuit;

a second interconnection electrically connecting said second P-type region to said P-well;

a third interconnection electrically connecting said second N-type region to said N-well;

a fourth interconnection electrically connecting said first N-type region to a discharge region of the SOI integrated circuit for shunting current associated with an ESD event being applied to said protected circuit through said first and second P-type regions and said intermediate region of said N-well, and through said first and second N-type regions and said intermediate region of said P-well, to said discharge region of the SOI integrated circuit;

fifth and sixth interconnections for connecting said first P-type region to one side of a first external resistive device, and said N-well to the other side of the first external resistive device; and

sixth and seventh interconnections for connecting said first N-type region to one side of a second external resistive device, and the other side of the second external resistive device to said P-well.