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Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics

  • US 6,016,000 A
  • Filed: 04/22/1998
  • Issued: 01/18/2000
  • Est. Priority Date: 04/22/1998
  • Status: Expired due to Fees
First Claim
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1. A multi-level interconnect structure for a semiconductor integrated circuit chip on a semiconductor substrate comprising:

  • a plurality of electrically conductive metallization levels, each of said metallization levels comprising a plurality of electrically conductive interconnect segments;

    a plurality of electrically conductive plugs for electrically connecting between various metallization levels and between said metallization levels and a plurality of semiconductor devices;

    a free-space medium occupying at least a substantial portion of the electrically insulating regions within said multi-level interconnect structure; and

    an electrically insulating top passivation overlayer for hermetic sealing of said multi-level interconnect structure and for protection of said integrated circuit chip, said top passivation overlayer also serving as a heat transfer medium for facilitating heat removal from said interconnect structure and providing additional mechanical support for said interconnect structure through contact with the top metallization level of said multi-level interconnect structure.

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