Class-D amplifier input structure

• US 6,016,075 A
• Filed: 06/04/1997
• Issued: 01/18/2000
• Est. Priority Date: 06/04/1997
• Status: Expired due to Fees

• Current Assignee: Lord Corporation (Parker-Hannifin Corporation)
• Original Assignee: Lord Corporation (Parker-Hannifin Corporation)
• Inventors: Hamo, David J.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US08/869,104
• Time in Patent Office: 958 Days
• Field of Search: 330/10, 330/207 A, 330/251, 381/120, 381/121
• US Class Current: 330/10
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/3061 Bridge type, i.e. two complementary controlled SEPP output stages

Abstract

A Class-D amplifier using an audio signal input structure with monolithic devices forming integrated circuit configurations to receive audio input signals to be amplified. One monolithic device used to couple audio input ports to receive respective audio input signals to be amplified and feedback network to receive feedback signals is a pulse-width-modulator. Another monolithic device is used to form an integrated circuit with a pulse-width-modulated square wave input ports. Field effect transistor driver circuits are connected to respective pulse-with-modulated square wave signal input ports. Filter circuits coupled to the integrated circuits are used to receive and filter the amplified square wave signals and produce continuous amplified audio signals.

Claims

1. An audio amplifier comprising:

(a) a first section having at least one audio signal input port to which a respective audio input signal to be amplified is applied;

(b) a second section having a first monolithic device forming an integrated circuit coupled to said respective audio input port to receive said respective audio input signal, coupled to at least one feedback network to receive a respective feedback signal from the respective output of said audio amplifier, and adapted to produce at least one Pulse Width Modulated square wave signal;

(c) a third section embodied in a second monolithic device forming a second integrated circuit having;

(i) at least one Pulse Width Modulated square wave signal input port;

(ii) at least two square wave signal output ports;

(iii) at least two field effect transistor (FET) driver circuits connected to said respective Pulse Width Modulated square wave signal input port to receive a respective Pulse Width Modulated square wave signal and develop therefrom a respective square wave FET switching signal directed to a respective said square wave signal output port;

(d) a fourth section having at least one FET operated switching circuit with at least two FETs wherein each of said FETs is connected to a corresponding respective square wave signal output port, each said respective FET being operative in response to a respective said square wave FET switching signal being received on the respective said square wave signal output to which said respective FET connected to switch sequentially and produce therefrom as an output of each said respective FET operated switching circuit a respective amplified square wave signal;

said fourth section being adapted for use in conjunction with a proscribed number of external power sources;

(e) a fifth section having;

(i) at least one filter circuit connected to receive and filter said respective amplified square wave signal, and produce therefrom a respective continuous amplified audio signal;

(ii) at least one audio speaker connected to receive said respective continuous amplified audio signal and produce a respective audible signal therefrom;

(f) said respective feedback network is coupled to said respective filter circuit and said respective audio input port for transmitting said respective feedback signal in which the formation of said respective Pulse Width Modulated square wave signal depends; and

wherein said first and second sections and the components thereof are embodied in a single integrated circuit adapted on its input side to receive said respective audio input signal and said respective feedback signal, and on its output side having connections to said respective FET switching circuit.

2. An audio amplifier claimed in claim 1, wherein:

(a) said proscribed number of power sources comprises a positive and negative power supply;

(b) said respective FET operated switching circuit comprises a half-bridge topology having;

(i) a p-channel FET having a source, a drain, and a gate, the source being connected to said positive power supply, the drain being connected to said respective filter circuit, the gate being connected to receive said respective square wave FET switching signal;

(ii) a n-channel FET having a source, a drain, and a gate, the source being connected to said negative power supply, the drain being connected to said respective filter circuit, the gate being connected to receive said respective square wave FET switching signal.

3. An audio amplifier claimed in claim 1, wherein:

(a) said proscribed number of power sources comprises a single positive power supply;

(b) said FET operated switching circuit comprises a full-bridge topology having;

(i) a first and second n-channel FET having a respective source, drain and gate, the respective sources of said first and second n-channel FETs connected to said respective filter circuit, the respective drains connected to said positive power supply, the respective gates connected to receive said respective square wave FET switching signal;

(ii) a third and fourth n-channel FET having a respective source, drain and gate, the respective sources of said third and fourth n-channel FETs connected to a ground plan, the respective drains connected to said respective filter circuit, the respective gates are connected to receive said respective square wave FET switching signal.

4. An audio amplifier claimed in claim 1, wherein:

(a) said proscribed number of power sources comprises a single positive power supply;

(b) said FET operated switching circuit comprises a half-bridge topology having first and second n-channel FETs having a respective source, drain and gate, wherein the drain of said first n-channel FET connected to said a single positive power supply, the source of said first FET and drain of said second FET coupled to said respective filter circuit, the respective gates said first and second FETs connected to receive said respective square wave FET switching signal;

(c) an output AC coupling capacitor coupled in series between said respective amplified square wave signal and said respective speaker.

7. An audio amplifier claimed in claim 1, wherein said respective filter comprises a inductance capacitor network.

5. An audio amplifier claimed in 4, wherein said AC coupling capacitor is coupled in circuit before said respective filter circuit.

6. An audio amplifier claimed in 4, wherein said AC coupling capacitor is coupled in circuit after said respective filter circuit.

8. A Class-D amplifier comprising:

(a) a first section having at least one signal input port to which a respective input signal to be amplified is applied;

(b) a second section comprising a power supply Pulse Width Modulated controller device as a first monolithic device forming an integrated circuit coupled to said respective input port to receive said respective input signal, coupled to at least one feedback network to receive a respective feedback signal from the respective output of said Class-D amplifier, and adapted to produce at least one Pulse Width Modulated square wave signal, the first monolithic device including an error amp coupled to the feedback signal and the input signal to produce an error signal responsive thereto;

(c) a third section embodied in a second monolithic device forming a second integrated circuit having;

(i) at least one Pulse Width Modulated square wave signal input port;

(ii) at least two square wave signal output ports;

(iii) at least two field effect transistor (FET) driver circuits connected to said respective Pulse Width Modulated square wave signal input port to receive a respective Pulse Width Modulated square wave signal and develop therefrom a respective square wave FET switching signal directed to a respective said square wave signal output port;

(d) a fourth section having at least one FET operated switching circuit with at least two FETs wherein each said FET is connected to a corresponding respective square wave signal output port, each said respective FET being operative in response to a respective said square wave FET switching signal being received on the respective said square wave signal output to which said respective FET connected to switch sequentially and produce therefrom as an output of each said respective FET operated switching circuit a respective amplified square wave signal;

said fourth section being adapted for use in conjunction with a proscribed number of external power sources; and

(e) wherein said respective feedback network is coupled to said respective amplified square wave signal.

9. A Class-D amplifier according to claim 8 further comprising a fifth section having:

(i) at least one filter circuit connected to receive and filter said respective amplified square wave signal, and produce therefrom a respective continuous amplified signal;

(ii) an output device connected to receive said respective continuous amplified signal.

10. A Class-D amplifier according to claim 9 wherein:

(a) said proscribed number of power sources comprises a positive and negative power supply;

(b) said respective FET operated switching circuit comprises a half-bridge topology having;

(i) a p-channel FET having a source, a drain, and a gate, the source being connected to said positive power supply, the drain being connected to said respective filter circuit, the gate being connected to receive said respective square wave FET switching signal;

(ii) a n-channel FET having a source, a drain, and a gate, the source being connected to said negative power supply, the drain being connected to said respective filter circuit, the gate being connected to receive said respective square wave FET switching signal.

11. A Class-D amplifier according to claim 9, wherein:

(a) said proscribed number of power sources comprises a single positive power supply;

(b) said FET operated switching circuit comprises a full-bridge topology having;

(i) a first and second n-channel FET having a respective source, drain and gate, the respective sources of said first and second n-channel FETs connected to said respective filter circuit, the respective drains connected to said positive power supply, the respective gates connected to receive said respective square wave FET switching signal;

(ii) a third and fourth n-channel FET having a respective source, drain and gate, the respective sources of said third and fourth n-channel FETs connected to a ground, the respective drains connected to said respective filter circuit, the respective gates connected to receive said respective square wave FET switching signal.

12. A Class-D amplifier according to claim 9, wherein:

(a) said proscribed number of power sources comprises a single positive power supply;

(b) said FET operated switching circuit comprises a half-bridge topology having first and second n-channel FETs having a respective source, drain and gate, wherein the drain of said first n-channel FET is connected to said single positive power supply, the source of said first FET and drain of said second FET coupled to said respective filter circuit, the respective gates of said first and second FETs connected to receive said respective square wave FET switching signal;

(c) an output AC coupling capacitor coupled in series between said respective amplified square wave signal and said respective output device.

13. A Class-D amplifier according to claim 12, wherein said AC coupling capacitor is coupled in circuit before said respective filter circuit.

14. A Class-D amplifier according to claim 12, wherein said AC coupling capacitor is coupled in circuit after said respective filter circuit.

15. A Class-D amplifier according to claim 8 further comprising an anti-thump circuit coupled to the first monolithic device and the amplified square wave signal.

16. A Class-D amplifier according to claim 15 wherein the first monolithic device includes a DTC control input and wherein the anti-thump circuit is connected to the DTC control input.

17. A Class-D amplifier according to claim 16 wherein the anti-thump circuit inverts the amplified square wave signal.