Method for manufacturing electro-optic element

• US 6,016,174 A
• Filed: 03/26/1998
• Issued: 01/18/2000
• Est. Priority Date: 03/27/1997
• Status: Expired due to Term

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Advanced Display Technologies
• Inventors: Endo, Yukio, Ogo, Ikuo, Nakamura, Nobuhiro
• Primary Examiner(s): Dudek, James A.
• Application Number:
  US09/048,093
• Time in Patent Office: 663 Days
• Field of Search: 349/43, 257/72, 257/59
• US Class Current: 349/43
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A method for manufacturing electo-optic elements includes steps of: (a-1) forming gate electrodes of the gate line and the TFT by patterning the first metal thin film by the first photolithography process after forming the first metal thin film on the first insulating substrate, (a-2) patterning by dry etching the semiconductor active film and the ohmic contact film by the second photolithography process in the larger and continuous form than the portion in which the source line and the TFT are formed after forming the first insulating film, semiconductor active film, and ohmic contact film, (a-3) patterning the second metal thin film by the third photolithography process after forming the second metal thin film to form the source electrode and the drain electrode of the source line as well as the TFT and in addition, etch-removing by dry etching the ohmic contact film protruding from the source line, source electrode, and drain electrode, (a-4) patterning the second insulating film and the first insulating film in the fourth photolithography process after forming the second insulating film, and forming a pixel contact hole that penetrates at least to the drain electrode surface, the first contact hole that penetrates to the first metal film surface, and the second contact hole that penetrates the second metal film surface, and (a-5) patterning the conductive thin film and forming the pixel electrode by the fifth photolithography process after forming the conductive thin film.

Claims

1. A method for manufacturing electro-optic elements including a first insulating substrate wherein a display pixel having a pixel electrode in which a TFT is electrically connected is formed as an array, a TFT array substrate wherein a gate line for sequentially scanning each TFT intersects at right angles a source line which provides a signal potential to the pixel electrode, and a second insulating substrate having an opposite substrate on which a color filter and a common electrode are formed, wherein the TFT array substrate and the opposite substrate are affixed with a liquid crystal layer interposed in-between and polarizers are placed at the top of the TFT array substrate and at the bottom of the opposite substrate, respectively, comprising the steps:

forming gate electrodes of the gate line and the TFT by patterning a first metal thin film by a first photolithography process after forming the first metal thin film on the first insulating substrate;

patterning by dry etching a semiconductor active film and an ohmic contact film by a second photolithography process wherein the semiconductor active film and the ohmic contact film are formed in a continuous shape and are larger than a portion in which the source line and the TFT are formed, wherein said patterning step occurs after forming a first insulating film, the semiconductor active film, and the ohmic contact film;

patterning a second metal thin film by a third photolithography process after forming the second metal thin film to form a source electrode and a drain electrode of the source line as well as the TFT and etch-removing by dry etching the ohmic contact film protruding from the source line, the source electrode, and the drain electrode, wherein the source electrode is formed on the gate line of the source line extending from a portion other than intersecting portions between the gate line and the source line;

patterning a second insulating film and the first insulating film in a fourth photolithography process after forming the second insulating film and forming a pixel contact hole that penetrates at least to the drain electrode surface, a first contact hole that penetrates to the first metal thin film surface, and a second contact hole that penetrates the second metal thin film surface; and

,

patterning a conductive thin film and forming the pixel electrode by a fifth photolithography process after forming the conductive thin film.

3. The method of claim 1 or claim 2 wherein auxiliary capacity to first and second display electrodes is formed between the first display electrode and the second display electrode via a dielectric substance in parallel with capacity formed between the pixel electrode and the common electrode via the liquid crystal layer, and either the first or the second display electrode is the pixel electrode and the dielectric substance is a laminated film including the first insulating film and the second insulating film.

4. The method of claim 3, wherein the other display electrode is an auxiliary capacity electrode, an auxiliary capacity line includes the first metal thin film, and the auxiliary capacity electrode and the auxiliary capacity line are formed simultaneously with the gate electrode and the gate line.

5. The method of claim 3, wherein the other display electrode is part of a gate line scanned one scanning period before a gate line for scanning the TFT connected to the pixel electrode.

6. The method of claim 4, wherein a display portion lead-out line is formed outside a display area with display pixels formed in an array, the display portion lead-out line includes a gate-side lead-out and a source-side lead-out line, a gate-side lead-out electrode connects a driver output connecting terminal including TCP loaded with a driver IC for installing to input a signal potential to the gate line, the source-side lead-out electrode connects the driver output connecting terminal of TCP loaded with the driver IC for providing to input the signal potential to the source line, the gate-side lead-out electrode is formed in a profile continuing from the gate line by patterning the first metal thin film, and the source-side lead-out electrode is formed in the profile continuing from the source line by patterning the second metal thin film.

7. The method of claim 6, wherein the driver output connecting terminal connecting to the gate-side lead-out line is constructed such that the first insulating film, the second insulating film, and the conductive thin film are laminated on the first metal thin film, the first metal thin film and the conductive thin film are electrically connected with the first contact hole, and the first contact hole is covered with an anisotropic conductive film which connects the TCP to the driver output connecting terminal on the gate line side;

and, the driver output connecting terminal connecting to the source-side lead-out line is constructed such that the first insulating film, the second metal thin film, the second insulating film, and the conductive thin film are laminated on the first metal thin film, the first metal thin film and the second metal thin film and the conductive thin film are electrically connected with the second contact hole, and the second contact hole is covered with the anistropic conductive film.

8. The method of claim 6, further comprising th steps;

forming a gate-side preliminary line which is a laminated structure by patterning the second metal thin film, the semiconductor active film, and the ohmic contact film to intersect with the gate-side lead-out line;

forming a counter-gate-side preliminary line which is a laminated structure by patterning the second metal thin film, the semiconductor active film, and the ohmic contact film on the side opposite to the side on which the gate-side lead-out line is formed;

forming a source-side preliminary line by patterning the first metal thin film to intersect with the source-side lead-out line; and

, forming a counter-source-side preliminary line by patterning the first metal thin film to intersect with the source line formed by extending on the side opposite to the side in which the source-side lead-out line in the display region is formed;

wherein the gate-side preliminary line, the source-side preliminary line, the counter-source-side preliminary line, and counter-gate-side preliminary line have portions partly overlapping one another in order to form the first contact hole and the second contact hole in the vicinity of the overlapping portions and to form the conductive thin film by patterning in such a manner as to electrically connect the first contact hole and the second contact hole.

9. The method of claim 5, wherein a display portion lead-out line is formed outside a display area with display pixels formed in an array, the display portion lead-out line includes a gate-side lead-out line and a source-side lead out line, a gate-side lead-out electrode connects a driver output connecting terminal including TCP loaded with a driver IC for installing to input a signal potential to the gate line, the source-side lead-out electrode connects the driver output connecting terminal of TCP loaded with the driver IC for providing to input the signal potential to the source line, the gate-side lea-out electrode is formed in a profile continuing from the gate line by patterning the first metal thin film, and the source-side lead-out electrode is formed in the profile continuing from the source line by patterning the second metal thin film.

2. A method for manufacturing electro-optic elements including a first insulating substrate wherein a display pixel having a pixel electrode in which a TFT is electrically connected is formed as an array, a TFT array substrate wherein a gate line for sequentially scanning each TFT intersects at right angles a source line which provides a signal potential to the pixel electrode, and a second insulating substrate having an opposite substrate on which a color filter and a common electrode are formed, wherein the TFT array substrate and the opposite substrate are affixed with a liquid crystal layer interposed in-between and polarizers are placed at the top of the TFT array substrate and at the bottom of the opposite substrate, respectively, comprising the steps:

forming gate electrodes of the gate line and the TFT by patterning a first metal thin film by a first photolithography process after forming the first metal thin film on the first insulating substrate;

patterning by dry etching a semiconductor active film and an ohmic contact film by a second photolithography process wherein the semiconductor active film and the ohmic contact film are formed in a continuous shape and are larger than a portion in which the source line and the TFT are formed, wherein said patterning step occurs after forming a first insulating film, the semiconductor active film, and the ohmic contact film;

patterning a second metal thin film by a third photolithography process after forming the second metal thin film to form a source electrode and a drain electrode of the source line as well as the TFT and etch-removing by dry etching the ohmic contact film protruding from the source line, the source electrode, and the drain electrode, wherein the source electrode is formed on the gate line of the source line extending from intersecting portions of the gate line and the source line;

patterning a second insulating film and the first insulating film in a fourth photolithography process after forming the second insulating film and forming a pixel contact hole that penetrates at least to the drain electrode surface, a first contact hole that penetrates to the first metal thin film surface, and a second contact hole that penetrates the second metal thin film surface; and

,

patterning a conductive thin film and forming the pixel electrode by a fifth photolithography process after forming the conductive thin film.