Voltage overshoot protection circuit

• US 6,016,245 A
• Filed: 03/13/1998
• Issued: 01/18/2000
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ross, Steven L.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US09/041,983
• Time in Patent Office: 676 Days
• Field of Search: 361/18, 361/79, 361/56, 361/86, 361/91, 361/87, 361/111, 361/93-94, 361/98-100, 361/101, 323/274-276, 323/280-281, 323/284-286
• US Class Current: 361/86
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: H02H 9/005 avoiding undesired transient conditions

Abstract

A voltage overshoot protection circuit includes an integration circuit configuration. The integration circuit configuration is included in the voltage overshoot protection circuit so as to integrate excess diverted current drawn from a bus. The voltage overshoot protection circuit is adapted to be electrically coupled to the bus.

Claims

1. A voltage overshoot protection circuit comprising:

an integration circuit configuration, said integration circuit configuration being included in said circuit so as to integrate excess diverted current drawn from a bus;

said protection circuit being adapted to be electrically coupled to the bus, the voltage overshoot protection circuit including circuitry to detect the voltage overshoot, the circuitry to detect the voltage overshoot including a bandgap voltage reference source;

wherein the voltage overshoot protection circuit is capable of being programmed for both the bus voltage signal level trip point and the amount of energy to be absorbed;

wherein the voltage overshoot protection circuit includes the capability to respond to a voltage overshoot within on the order of a few microseconds.

2. The voltage overshoot protection circuit of claim 1, wherein the voltage overshoot protection circuit is capable of being programmed for both the bus voltage signal level trip point and the amount of energy to be absorbed by changing only an external resistor or/and capacitor.

3. The voltage overshoot protection circuit of claim 2, wherein:

the integration circuit configuration comprises an operational amplifier integration circuit configuration.

4. The voltage overshoot protection circuit of claim 3, and further comprising:

a transistor configuration coupled in the voltage overshoot protection circuit so that the excess current diverted from the bus flows therethrough.

5. The voltage overshoot protection circuit of claim 4, wherein:

the transistor configuration comprises a darlington pair transistor configuration.

6. The voltage overshoot protection circuit of claim 2, and further comprising a comparator circuit configuration coupled to receive an output signal of the integration circuit configuration and responsive thereto.

7. A voltage overshoot protection circuit comprising:

a metal-oxide semiconductor field effect transistor (MOSFET) integration circuit configuration,

said integration circuit configuration being included in said circuit so as to integrate a voltage related to excess diverted current drawn from a bus;

said protection circuit being adapted to be electrically coupled to the bus;

the voltage overshoot protection circuit including circuitry to detect the voltage overshoot, the circuitry to detect the voltage overshoot including a bandgap voltage reference source;

wherein the voltage overshoot protection circuit is capable of being programmed for both the bus voltage signal level trip point and the amount of energy to be absorbed;

wherein the voltage overshoot protection circuit includes the capability to respond to a voltage overshoot within on the order of a few microseconds.

8. A computing system comprising:

a voltage overshoot protection circuit, said voltage overshoot protection circuit being adapted to be coupled to a bus;

a transistor configuration coupled in said voltage overshoot protection circuit to receive excess current diverted from said bus;

an integration circuit coupled to said transistor configuration to integrate the amount of excess current diverted from said bus through said transistor configuration; and

said voltage overshoot protection circuit being adapted to disable a power source based, at least in part, on the integrated amount of excess diverted current from said bus,

wherein the voltage overshoot protection circuit includes circuitry to detect the voltage overshoot, the voltage overshoot detection circuitry including a bandgap precision voltage reference source;

wherein the voltage overshoot protection circuit is capable of being programmed for both the bus voltage signal level trip point and the amount of energy to be absorbed;

wherein the voltage overshoot protection circuit includes the capability to respond to a voltage overshoot within on the order of a few microseconds.

9. The computing system of claim 8, wherein the voltage overshoot protection circuit is capable of being programmed for both the bus voltage signal level trip point and the amount of energy to be absorbed by changing only an external resistor or/and capacitor.

10. The computing system of claim 9, wherein:

the integration circuit configuration comprises an operational amplifier integration circuit configuration.

11. The computing system of claim 10, wherein:

the transistor configuration comprises a darlington pair transistor configuration.

12. A computing system comprising:

a voltage overshoot protection circuit, said voltage overshoot protection circuit being adapted to be coupled to a bus;

a metal-oxide semiconductor field effect transistor (MOSFET) integration circuit configuration;

said integration circuit configuration being coupled so as to integrate a voltage related to excess current diverted from said bus;

said voltage overshoot protection circuit being adapted to disable a power source based, at least in part, on the integrated voltage;

wherein the voltage overshoot protection circuit includes circuitry to detect the voltage overshoot, the voltage overshoot detection circuitry including a bandgap precision voltage reference source;

wherein the voltage overshoot protection circuit is capable of being programmed for both the bus voltage signal level trip point and the amount of energy to be absorbed;

wherein the voltage overshoot protection circuit includes the capability to respond to a voltage overshoot within on the order of a few microseconds.

13. A method of diverting excess current through a voltage overprotection circuit comprising:

activating a diversion path for the excess current when the voltage level of a supply bus achieves a substantially predetermined level so that the voltage of the supply bus is substantially maintained within substantially predetermined voltage level bounds;

comparing the voltage level of the supply bus with a bandgap precision voltage reference to determine whether the voltage level of the supply bus has achieved the substantially predetermined level; and

performing an operation upon reaching a substantially predetermined amount of diverted excess current;

wherein the voltage overprotection circuit includes the capability to respond to a voltage overshoot within on the order of a few microseconds; and

wherein the substantially predetermined voltage level and the substantially predetermined amount of diverted excess current were programmed.

14. The method of claim 13, wherein the substantially predetermined voltage level and the substantially predetermined amount of diverted excess current were programmed by changing only an external resistor or/and capacitor.

15. The method of claim 14, wherein:

performing an operation includes integrating the diverted excess current flowing through the diversion path to determine the amount of diverted excess current flowing through the diversion path.

16. The method of claim 15, wherein:

performing an operation includes disabling a source power supply when the integrated diverted excess current achieves the substantially predetermined amount.