Flash memory wear leveling system and method

• US 6,016,275 A
• Filed: 11/04/1998
• Issued: 01/18/2000
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Han, Sang-Wook
• Primary Examiner(s): Yoo, Do Hyun
• Application Number:
  US09/185,709
• Time in Patent Office: 440 Days
• Field of Search: 365/185.29, 365/218, 365/189.07, 365/185.33
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

A wear leveling system and method of a flash memory cell uses the amount of time required to perform an erasing operation on a sector of the flash memory to determine whether the memory cells in the sector have degraded to an unacceptable level. The actual time required to erase a sector of a flash memory array is compared to a reference erasing time required to erase a unit sector under the state of the worst allowable degradation. If the actual erasing time of a sector exceeds the reference erasing time, logical addresses corresponding to the sector are re-mapped to the physical addresses of a different sector. On the other hand, when the actual erasing time is shorter than or equal to the reference erasing time, a controller continues to use the unit sector.

Claims

1. A method of wear leveling a flash memory cell array, comprising the steps of:

detecting the time required to complete an erasing operation on a sector of the memory cell array; and

determining whether to continue using the sector based on the detected erasing time.

2. The method of claim 1, wherein the determining step comprises:

comparing the detected erasing time to a reference erasing time.

3. The method of claim 2, wherein the determining step further comprises determining that the sector should not be used if the detected erasing time exceeds the reference erasing time.

4. The method of claim 3, wherein the determining step further comprises determining that the sector should continue to be used if the detected erasing time is equal to or less than the reference erasing time.

5. The method of claim 3, further comprising the step of re-mapping the memory cell array if the detected erasing time exceeds the reference erasing time.

6. The method of claim 5, wherein the remapping step comprises assigning a logical address that corresponded to the sector to the physical address of a different sector.

7. The method of claim 1, wherein the detecting step comprises detecting the time required to erase all memory cells of the sector.

8. A wear leveling system of a flash memory cell array, comprising:

a detector configured to detect an amount of time required for memory cells of a sector of said flash memory cell array to be erased; and

a comparator configured to compare a reference erasing time to said detected erasing time.

9. The system of claim 8, wherein said reference erasing time is a time required for all memory cells of a sector to be erased under the state of the worst allowable degradation.

10. The system of claim 8, further comprising an address converter configured to convert logical addresses to physical addresses of the memory cell array.

11. The system of claim 10, wherein the address converter is also configured to re-map a logical address corresponding to the physical address of a first sector to the physical address of a second sector when the detected erasing time of the first sector is longer than said reference erasing time.

12. The system of claim 8, wherein the system is configured such that when an erasing time of a sector exceeds the reference erasing time, the sector is no longer used to store data.

13. A wear leveling method of a flash memory cell array having at least one sector, comprising the steps of:

detecting a data erasing time of a sector in said flash memory cell array; and

comparing the detected data erasing time to a predetermined reference erasing time to check the wear status of the sector.

14. The method of claim 13, wherein said wear leveling method further comprises the steps of:

converting a logical address generated in a host to a physical address of the memory cell array;

erasing data stored in the sector corresponding to the physical address; and

re-mapping the logical address to a new physical address of an available sector when said detected erasing time is longer than said reference erasing time.

15. The method of claim 14, wherein said reference erasing time is the time required to erase all memory cells of a sector under the state of the worst allowable degradation.

16. The method of claim 13, further comprising the step of re-mapping the memory cell array if the detected erasing time exceeds the reference erasing time.

17. A method of wear leveling a flash memory cell array, comprising the steps of:

detecting a time required to erase data from memory cells of a sector of the memory cell array; and

re-mapping the memory cell array if the detected erasing time exceeds a predetermined reference erasing time so that the sector is no longer used to store data.

18. The method of claim 17, wherein the re-mapping step comprises reassigning a logical address corresponding to a physical address of the sector to a new physical address of an available sector.

19. The method of claim 17, wherein during the detecting step, all memory cells in the sector are erased substantially simultaneously.