Low distortion audio muting circuit

• US 6,016,352 A
• Filed: 11/20/1997
• Issued: 01/18/2000
• Est. Priority Date: 11/20/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Barmore, Bradley Allen
• Primary Examiner(s): Lee, Ping
• Application Number:
  US08/974,974
• Time in Patent Office: 789 Days
• Field of Search: 381/94.5, 381/104, 381/109, 381/102, 455/200.1, 330/51
• US Class Current: 381/94.5
• CPC Class Codes: H03G 3/348 Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits

Abstract

A muting circuit is provided to mute an audio signal at an audio output. The muting circuit includes a switching device having an enable input and being adapted to be coupled between an audio output and ground, the switching device being on when the enable input is at a deenergized voltage level. A mute controller is coupled to receive a mute signal and provide a signal to the enable input of the switching device to bias the switching device on.

Claims

1. A muting circuit comprising:

a switching device having an enable input and being adapted to be coupled between an audio output and ground, the switching device being on when the enable input is at a deenergized voltage level; and

a mute controller coupled to receive a mute signal and provide a signal to the enable input of the switching device to bias the switching device on, the mute controller including;

an open collector buffer having an input and output, the input being coupled to receive the mute signal,

a transistor having an enable input, the transistor coupled between ground and the enable input of the switching device,

a first resistor coupled between a first voltage source and the enable input of the switching device,

a second resistor coupled between the output of the open collector buffer and the enable input of the transistor,

a third resistor coupled between the enable input of the transistor and a second voltage source, and

a fourth resistor coupled between the output of the open collector buffer and a third voltage source.

2. The muting circuit of claim 1, wherein the first and second voltage sources provide substantially negative twelve volts.

3. The muting circuit of claim 1, wherein the third voltage source provides substantially five volts.

4. The muting circuit of claim 3, wherein the third voltage source is a standby voltage source.

5. The muting circuit of claim 1, wherein the switching device comprises a junction field effect transistor (JFET).

6. The muting circuit of claim 5, wherein the JFET comprises an n-channel JFET.

7. The muting circuit of claim 5, wherein the JFET comprises a p-channel JFET.

8. The muting circuit of claim 1, wherein the switching device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET).

9. A muting circuit for an audio system having a plurality of audio outputs, comprising:

a plurality of switching devices, each of the plurality of switching devices having an enable input and being adapted to be coupled between an audio output of the plurality of audio outputs and ground, each of the plurality of switching devices being on when the enable input is at a deenergized voltage level; and

a mute controller coupled to receive a mute signal and provide a signal to the enable inputs of the plurality of switching devices to bias each of the plurality of switching devices on, the mute controller including;

an open collector buffer having an input and output, the input being coupled to receive the mute signal,

a transistors having an enable input, the transistor coupled between ground and the enable inputs of the plurality of switching devices,

a first resistor coupled between a first voltage source and the enable inputs of the plurality of switching devices,

a second resistor coupled between the output of the open collector buffer and the enable input of the transistor,

a third resistor coupled between the enable input of the transistor and a second voltage source, and

a fourth resistor coupled between the output of the open collector buffer and a third voltage source.

10. The muting circuit of claim 9, wherein the first and second voltage sources provide substantially negative twelve volts.

11. The muting circuit of claim 9, wherein the third voltage source provides substantially five volts.

12. The muting circuit of claim 11, wherein the third voltage source is a standby voltage source.

13. The muting circuit of claim 9, wherein one or more of the plurality of switching devices comprise a junction field effect transistor (JFET).

14. The muting circuit of claim 13, wherein the JFET comprises an n-channel JFET.

15. The muting circuit of claim 13, wherein the JFET comprises a p-channel JFET.

16. The muting circuit of claim 9, wherein one or more of the plurality of switching devices comprises a metal-oxide-semiconductor field-effect transistor (MOSFET).