Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor

• US 6,016,395 A
• Filed: 10/18/1996
• Issued: 01/18/2000
• Est. Priority Date: 10/18/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Mohamed, Moataz Ali
• Primary Examiner(s): Hafiz, Tariq R.
• Assistant Examiner(s): Chaki, Kakali
• Application Number:
  US08/731,455
• Time in Patent Office: 1,187 Days
• Field of Search: 395/705, 395/706, 395/707, 395/708, 395/709, 712/1, 712/2, 712/3, 712/4, 712/5, 712/6, 712/7, 712/8, 712/9, 712/10
• US Class Current: 717/149
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask

Abstract

The present invention provides a new programming language which. is a superset of C++ optimized for writing vectorized dual-threaded programs on the MSP media processor. This invention discloses novel language constructs in the syntax and semantics to facilitate efficient programming and the generation of optimized efficient MSP object code. We have invented in VIVID new data types such as VECTOR and GMASK as well as new operators that map directly into the MSP instruction set such as @shfl, @avg, etc. We have also extended C++ to facilitate dual-threaded execution by exposing the MSP'"'"'s fork-join model to the VIVID programmer via. adding fork-join constructs to VIVID. We have also invented a syntax and semantics to facilitate having multiple returned results from a vector operation such as VD @@ VC=VA @shfl VB.

Claims

1. A method for creating a computer program on a computer readable media for execution by a vector processor, the method comprising:

a computer system reading a computer program written in a superset of C programming language, wherein the C programming language defines a plurality of operations and does not specify for each operation in said plurality how the operation is to be implemented in the vector processor, the computer program further including;

a declaration of a value having a vector type, the vector type being part of a programming model of the vector processor, the vector type being distinct from an array type included in the C programming language; and

a first operation having the vector type value as an operand, the first operation corresponding to a vector processor instruction VPI1 that can be executed by the vector processor and that has at least a vector operand; and

the computer system generating one or more vector processor instructions that together implement the first operation, the one or more instructions including one or more VPI1 instructions.

2. The method of claim 1, wherein said high level language does not specify for each value whether the value is to be stored in a register of the vector processor or in a memory external to the vector processor.

3. The method of claim 1, wherein the program does not specify how the vector type value is to be stored.

4. The method of claim 1, wherein:

the computer program further includes declaration of a selection mask; and

the first vector operation is subjected to the selection mask to determine which elements of the vector operand are operated upon.

5. The method of claim 4 wherein:

the first operation does not have the selection mask as an operand.

6. The method of claim 4 wherein:

the first operation is a vector ALU operation; and

each bit in the selection mask indicates if a corresponding element of the vector operand is affected by the first operation.

7. The method of claim 4 wherein:

the first operation is a memory access operation; and

each bit in the selection mask indicates if a corresponding element of the vector operand is affected by the first operation.

8. The method of claim 1, wherein said first operation comprises one or more arithmetic operations.

9. The method of claim 1 wherein a destination of the first operation has a plurality of operands.

10. The method of claim 1, wherein said first operation comprises one or more matrix operands.

11. The method of claim 1, wherein said first operation comprises one or more 9-bit operands.

12. The method of claim 1, wherein said superset includes the C++ programming language.

13. The method of claim 1, wherein said computer system comprises a control processor, the vector processor and a cache memory coupling said control processor to said vector processor.

14. The method of claim 13, wherein the control processor signals the vector processor to start execution, but the vector processor cannot cause the control processor to start execution.

15. The method of claim 1 wherein:

the value is included in a structure type of the C programming language.

16. The method of claim 1, wherein:

the value is a pointer.

17. The method of claim 16, wherein:

the first operation passes the pointer as an argument to a function.

18. The method of claim 1, wherein:

the vector operand is hereinafter referred to as VA; and

the first operation indicates calculation of the average of each element of VA with index value i with the element having an index value of i+1 and storing the average in the element having an index value of i of a result vector.

19. The method of claim 18, wherein:

the vector operand is hereinafter referred to as VA;

the first operation has another vector operand VB; and

the first operation indicates calculation of the average of each element of VA having an index value i with the element of VA having index value i+1 and the elements of VB having index values i amd i+1 and storing the average in element having index value of i of a result vector.

20. The method of claim 1, wherein:

the first operation is a logical operation selected from a group consisting of AND, OR and NOR.

21. The method of claim 1, wherein:

the first operation is a shift operation with a scalar operand s that indicates the number of bits to be shifted, and the shift operation being selected from a group consisting of left shift and right shift.

22. The method of claim 1, wherein the first operation is selected from a group consisting of:

a max exchange operation;

an extract sign operation; and

a count leading zeros operation.

23. The method of claim 1, wherein:

the first operation has a scalar operand i; and

the first operation divides the vector operand by 2ⁱ and stores the result in another vector operand.

24. The method of claim 1, wherein:

the vector operand is hereinafter referred to as VA;

the first operation also has a scalar operand i; and

the first operation extracts the ith element of vector VA and stores the result into another scalar operand.

25. The method of claim 1, wherein:

the vector operand is hereinafter referred to as VA;

the first operation has additional vector operands VB, VC and VD; and

the first operation indicates multiplication of each element of VA by the corresponding element of VB, then addition of the corresponding element of VC to the double precision result of the multiplication and storing the double precision result of the addition in the corresponding element of VD.

26. The method of claim 1, wherein:

the vector operand is hereinafter referred to as VA;

the first operation stores the result into another vector operand VC in an element j that is different from an element i of VA.

28. The method of claim 26, wherein:

the first operation has additional vector operands VB and VD; and

the first operation unshuffles the elements of vector VA and VB and stores the result in vectors VC and VD.

29. The method of claim 26 wherein:

the first operation has an additional vector operand VB; and

the first operation is specified in the computer program by an operator located between VA and VB.

30. The method of claim 1, wherein the first operation is selected from a group consisting of:

a multiply and add operation;

an add and add sign operation; and

an add horizontal operation.

31. The method of claim 30, wherein:

the first operation is specified in the computer program by an operator located between the vector operand and another operand.

32. The method of claim 1, wherein:

the declaration includes an initialization of the vector operand, the initialization being specified by use of the "=" sign, followed by a plurality of values for elements in the vector operand, the plurality of values being enclosed within the "{" and "}" signs.

33. The method of claim 1 wherein:

the first operation is specified in the computer program by an operator located between the vector operand and another operand.

34. The method of claim 33 wherein:

the operator includes a predetermined symbol followed by at least one letter of the English language, the predetermined symbol being not included in the C programming language.

35. The method of claim 33 wherein:

the superset has a grammar that extends the grammar of the ANSI standard of C language.

27. The method of clam 26, wherein:

the first operation has additional vector operands VB and VD; and

the first operation shuffles the elements of vector VA and VB and stores the result in vectors VC and VD.