High speed network interface having SAR plus physical interface

• US 6,016,401 A
• Filed: 09/22/1997
• Issued: 01/18/2000
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Desai, Sanjay, Daane, John P., Stelliga, D. Tony, Rostoker, Michael D.
• Primary Examiner(s): Rinehart, Mark H.
• Application Number:
  US08/934,684
• Time in Patent Office: 848 Days
• Field of Search: 395/800.29, 395/800.3, 395/200.3, 395/200.64, 395/309, 395/200.8, 395/200.76, 395/250, 395/200.81, 364/DIG. 1, 364/DIG. 2, 370/401, 370/402, 370/403, 370/404, 370/463
• US Class Current: 712/29
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 using an external memory or storage device
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A single chip network interface apparatus includes a host interface circuit for communication with a host system bus, a network interface circuit for interfacing with a network bus, a dual port RAM coupled to the host interface circuit and also coupled to the network interface circuit, and a processor coupled to the dual port ram for converting packets of information between network protocol format and a format suitable for the host system bus.

Claims

1. A single chip network apparatus comprising:

a host interface circuit adapted for connection directly to a host system bus, the host interface circuit being operative to send information to and receive information from the host system bus;

random access memory coupled to the host interface circuit;

a multi-port random access memory coupled to the host interface circuit;

a processor coupled to the random access memory for formatting information received from the host system bus to a network protocol format, and for converting information received in a network, protocol format to a form suitable for the host system bus; and

a network interface circuit coupled to the random access memory and adapted for connection directly to a network the network interface circuit being operative to send and receive information from the network where such information is in a network protocol format.