Apparatus for controlling duty ratio of power saving of CPU

• US 6,016,548 A
• Filed: 07/15/1997
• Issued: 01/18/2000
• Est. Priority Date: 12/28/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Nobutaka, Yamaki, Masayo
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): JEAN, FRANTZ B
• Application Number:
  US08/893,926
• Time in Patent Office: 917 Days
• Field of Search: 395/750.04, 395/750.05, 395/550, 395/551, 395/750, 395/733, 395/734, 395/739, 395/740, 713/321, 713/322, 713/501, 713/503, 713/323, 711/101, 327/544, 307/125, 375/354, 710/266, 710/267, 710/261, 710/260
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a timer. The stop grant state is an intermediate power consumption state between the sleep mode and the normal state. The timer may include a software system management interrupt timer. The system may also include processing to determine the cause of the switch from the stop grant state to the normal state.

Claims

1. A computer system, comprising:

an external clock generator for generating an external clock signal having a first clock speed;

a central processing unit (CPU) for receiving the external clock signal and comprising an internal clock generator for generating an internal clock signal having a second clock speed based on the external clock signal, the second clock speed being the same as or faster than the first clock speed;

a timer for producing a time-out signal in accordance with a timing value in order to control power saving of the CPU;

first means for setting the timer with a first timing value and for switching the CPU from a normal state in which the external and the internal clock signals are running and commands are executable to a stop grant state in which the external and the internal clock signals are running, supply of the internal clock signal to internal logics of the CPU is stopped, and no command is executable in response to a first-time out signal from the timer; and

second means for setting the timer with a second timing value and for switching the CPU from the stop grant state to the normal state in response to a second time-out signal from the timer, thereby the first means and the second means repetitively and intermittently switching the CPU between the normal state and the stop grant state.

2. The system according to claim 1, further comprising a second timer for causing the CPU to save power in response to a time-out signal of the second timer.

3. The system according to claim 2, wherein the second timer is a global standby timer in which a third timing value is set for switching the CPU from a normal mode to control Dower saving of the CPU, and for producing a global standby time out signal.

4. The system according to claim 2, further comprising:

first determining means for, when a stop break is caused which causes the second means to switch the CPU from the stop grant state to the normal state, determining a cause of the stop break;

second determining means for, if the first determining means determines that the cause of the stop break is due to the stop break other than the software SMI, determining whether or not the stop break is due to a system timer interrupt; and

means for setting the second timer with a third timing value for switching the CPU from the normal mode to control power saving of the CPU, if the second determining means determines that the cause of the stop break is not due to the system timer interrupt.

5. The system according to claim 1, wherein the timer is a software system management interrupt (SMI) timer in which the first timing value and the second timing value are alternatively set for switching the CPU between the normal state and the stop grant state, and for producing a software SMI timer time out signal.

6. The system according to claim 1, further comprising:

means for, when a stop break is caused which causes the second means to switch the CPU from the stop grant state to the normal state, determining a cause of the stop break; and

means for setting the timer with the first timing value for causing the first means to switch the CPU from the normal state to the stop grant state if the determining means determines that the cause of the stop break is due to the timer time out signal.

7. The system according to claim 1, further comprising:

first determining means for, when a stop break is caused which causes the second means to switch the CPU from the stop grant state to the normal state, determining a cause of the stop break;

second determining means for, if the first determining means determines that the cause of the stop break is due to the stop break other than the time-out signal of the timer, determining whether or not the stop break is due to a system timer interrupt; and

means for setting the timer with the first timing value for causing the first means to switch the CPU from the normal state to the stop grant state if the second determining means determines that the stop break is due to the system timer interrupt.

8. The system according to claim 7, wherein the second determining means determines that the cause of the stop break is due to a system event if the cause of the stop break is not due to the system timer interrupt.

9. The system according to claim 1, wherein the stop grant state is a state in which an internal clock of the CPU is stopped.

10. A computer system comprising:

a CPU coupled to receive a periodic signal from a source external to the CPU that sets the CPU in a stop grant state in which an external clock and an internal clock are running and supply of the internal clock of the CPU to internal logics of the CPU is stopped and no command is executed; and

means for periodically asserting the periodic signal to set the CPU in the stop-grant state and changing a duty ratio of the periodic signal, thereby decreasing power consumption of the CPU.

11. The computer system according to claim 10, further comprising a programmable time-out counter for producing a first time-out signal which causes the CPU to transition from a normal state in which the external clock and the internal clock are running and commands are executable to the stop grant state and a second time-out signal which causes the CPU to transition from the stop grant state to the normal state.

12. The system according to claim 11, further comprising:

determining means for, when a stop break is caused which causes the CPU to transition from the stop grant state to the normal state, determining a cause of the stop break; and

means for setting the CPU to a normal mode to execute an interrupt process if the determining means determines that the cause of the stop break is an interrupt due to a system event.

13. The system according to claim 12, further comprising means for executing a process of a system timer interrupt if the determining means determines that cause of the stop break is due to a system timer interrupt.

14. A computer comprising:

a circuit device coupled to receive a signal from a source external to the circuit device that stops a supply of an internal clock of the circuit device to internal circuits of the circuit device, wherein the circuit device enters a low power state when it receives the signal;

means for asserting the signal to set the circuit device in the low power state; and

means for controlling an operational duty ratio of the circuit device by setting a time period for asserting the signal, wherein the circuit device has operational states including a normal state in which an instruction is executed, and a stop grant state in which a supply of the internal clock to the internal circuits is stopped and an instruction is not executed, the device transitions from the normal state to the stop grant state in response to the generation of a clock stop signal and transitions from the stop grant state to the normal state in response to stopping the generation of the clock stop signal, and the control means intermittently supplies the clock stop signal to the circuit device to set the circuit device to the stop grant state, and causes the circuit device to alternate between the normal state and the stop grant state at predetermined time intervals, to thereby cause the circuit device to alternate between the normal state and the stop grant state at the predetermined time intervals.

15. The computer system according to claim 14, further comprising a programmable time-out counter for producing a first time-out signal which causes the CPU to transition from a normal state to a stop grant state and a second time-out signal which causes the CPU to transition from the stop grant state to the normal state.

16. The system according to claim 14, further comprising:

determining means for, when a stop break is caused which causes the second means to switch the CPU from the stop grant state to the normal state, determining the cause of the stop break; and

means for setting the CPU to a normal mode to execute an interrupt process if the determining means determines that the cause of the stop break is an interrupt due to a system event.

17. The system according to claim 16, further comprising means for executing a process of a system timer interrupt if the determining means determines that the cause of the stop break is due to a system timer interrupt.