Method for event-related functional testing of a microprocessor

• US 6,016,554 A
• Filed: 07/28/1997
• Issued: 01/18/2000
• Est. Priority Date: 07/28/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Skrovan, Joseph C., Parker, Allan
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elisca, Pierre E.
• Application Number:
  US08/901,576
• Time in Patent Office: 904 Days
• Field of Search: 395/183.01, 395/183.04, 395/183.1, 395/183.13, 395/183.14, 395/183.15, 395/182.06, 395/182.21, 395/185.08, 395/500, 371/22.31, 371/25.1, 364/576, 364/232.3, 364/232.8, 714/720
• US Class Current: 714/25
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method is presented for event-related functional testing of a microprocessor. A model of the microprocessor is adapted to produce a trigger event, perform a target activity, and respond to a control signal. The target activity occurs over several system clock signal cycles. A control signal generator receives the trigger event and generates the control signal a selectable number of clock cycles (i.e., a delay time) after the trigger event. A testing program includes a program loop which causes the microprocessor model to produce the trigger event, perform the target activity to produce a test result, and compare the test result to an expected result. The program loop is repeatedly executed until the microprocessor model responds to the control signal during each clock cycle of the target activity. If the test result matches the expected result during each execution of the program loop, the microprocessor properly responds to the control signal during the target activity. The microprocessor model may be a software or hardware implementation. Software embodiments of a bus model, a memory model, and a test engine provide an operating environment for the microprocessor model. A microprocessor testing system includes a central processing unit (CPU), chip set logic, a system bus, a memory bus, and a memory unit. In a first embodiment of the testing system, the microprocessor model, the bus model, the memory model, and the test engine reside within the memory unit. In a second embodiment, the microprocessor model is a separate hardware implementation.

Claims

1. A method for performing functional testing upon a microprocessor, comprising:

providing a model of the microprocessor adapted to perform an activity of interest and to respond to a control signal, and wherein the activity of interest occurs over a plurality of clock cycles;

producing a trigger event signal from the microprocessor model prior to initiating performance of the activity of interest;

using the trigger event signal to generate the control signal during one of the plurality of clock cycles such that the microprocessor model responds to the control signal;

comparing a test result produced during the activity of interest to an expected result;

repeating the producing, using, and comparing steps until the microprocessor model has responded to the control signal during each of the plurality of clock cycles occurring during the activity of interest; and

verifying proper operation of the microprocessor during the activity of interest by matching the test result to the expected result during each execution of the comparing step.

2. The method as recited in claim 1, wherein the activity of interest comprises at least one activity of a plurality of activities which occur within the microprocessor.

3. The method as recited in claim 1, wherein the activity of interest is initiated by an instruction forwarded to the microprocessor model.

4. The method as recited in claim 1, wherein the control signal comprises an interrupt signal or a bus arbitration signal.

5. The method as recited in claim 1, wherein the trigger event signal is a predetermined combination of address, data, and control signals.

6. The method as recited in claim 1, wherein the occurrence of the trigger event signal indicates initiation of the activity of interest.

7. The method as recited in claim 1, wherein the using step comprises providing a control signal generator operably coupled to receive the trigger event signal and configured to produce the control signal in response to the trigger event signal.

8. The method as recited in claim 7, wherein a system clock signal is coupled to the microprocessor model and to the control signal generator.

9. The method as recited in claim 8, wherein the control signal generator produces the control signal a selectable number of cycles of the system clock signal after receiving the trigger event signal.

10. A method of performing functional testing upon a microprocessor, comprising:

providing a model of the microprocessor, wherein the microprocessor model is coupled to receive a control signal, and wherein the microprocessor model is configured to produce a trigger event signal, to perform an activity of interest, and to respond to the control signal, and wherein the activity of interest occurs over a plurality of clock cycles;

providing a control signal generator, wherein the control signal generator is coupled to receive the trigger event signal and is configured to generate the control signal in response to the trigger event signal; and

initiating execution of a testing program by the microprocessor model, wherein the testing program includes a program loop which causes the microprocessor model to produce the trigger event signal, to perform the activity of interest in order to produce a test result, and to compare the test result to an expected result, and wherein the program loop is repeatedly executed as long as the test result matches the expected result and until the microprocessor model responds to the control signal during each of the plurality of clock cycles of the activity of interest, and wherein successful completion of the testing program demonstrates proper operation of the microprocessor when responding to the control signal while performing the activity of interest.

11. The method as recited in claim 10, wherein the microprocessor model comprises a file consisting essentially of a list of operational elements, interconnection between the elements, and a plurality of instructions configured to exercise the elements.

12. The method as recited in claim 10, wherein the activity of interest comprises at least one activity of a plurality of activities which occur within the microprocessor.

13. The method as recited in claim 10, wherein the activity of interest is initiated by an instruction forwarded to the microprocessor model.

14. The method as recited in claim 10, wherein the control signal comprises an interrupt signal or a bus arbitration signal.

15. The method as recited in claim 10, wherein the trigger event signal is a predetermined combination of address, data, and control signals.

16. The method as recited in claim 10, wherein the occurrence of the trigger event signal indicates initiation of the activity of interest.

17. The method as recited in claim 10, wherein the control signal generator comprises a file consisting essentially of a list of operational elements, interconnection between the elements, and a plurality of instructions configured to exercise the elements.

18. The method as recited in claim 10, wherein a system clock signal is coupled to the microprocessor model and to the control signal generator.

19. The method as recited in claim 18, wherein the control signal generator is configured to generate the control signal a selectable number of clock cycles after receiving the trigger event signal.

20. A method of performing functional testing upon a microprocessor, comprising:

providing a model of the microprocessor, wherein the microprocessor model is coupled to receive a control signal, and wherein the microprocessor model is configured to produce a trigger event signal, to perform an activity of interest, and to respond to the control signal, and wherein the activity of interest occurs over a plurality of clock cycles;

providing a control signal generator, wherein the control signal generator is coupled to receive the trigger event signal and is configurable to generate the control signal a selectable delay time after-receiving the trigger event signal, and wherein the delay time is measured in clock cycles;

determining an initial value of the delay time such that the control signal generator will produce the control signal during the first of the plurality of clock cycles;

configuring the control signal generator to generate the control signal the delay time after receiving the trigger event signal;

producing the trigger event signal from the microprocessor model prior to initiating performance of the activity of interest in order to produce a test result;

comparing the test result to an expected result;

incrementing the delay time and repeating the configuring, producing, and comparing steps if the test result matches the expected result and until the microprocessor model responds to the control signal during each of the plurality of clock cycles of the activity of interest; and

verifying proper operation of the microprocessor while performing the activity of interest if the test result matches the expected result during each execution of the comparing step.

21. The method as recited in claim 20, wherein the microprocessor model comprises a file consisting essentially of a list of operational elements, interconnection between the elements, and a plurality of instructions configured to exercise the elements.

22. The method as recited in claim 20, wherein the activity of interest comprises at least one activity of a plurality of activities which occur within the microprocessor.

23. The method as recited in claim 20, wherein the activity of interest is initiated by an instruction forwarded to the microprocessor model.

24. The method as recited in claim 20, wherein the control signal comprises an interrupt signal or a bus arbitration signal.

25. The method as recited in claim 20, wherein the trigger event signal is a predetermined combination of address, data, and control signals.

26. The method as recited in claim 20, wherein the determining step is accomplished by determining the number of system clock signal cycles between the trigger event signal and the first of the plurality of clock cycles of the activity of interest.

27. The method as recited in claim 26, wherein the trigger event signal occurs during the first of the plurality of clock cycles of the activity of interest, and the initial value of the delay time is therefore `0`.

28. The method as recited in claim 20, wherein the control signal generator comprises a file consisting essentially of a list of operational elements, interconnection between the elements, and a plurality of instructions configured to exercise the elements.

29. The method as recited in claim 20, wherein the control signal generator comprises an addressable control register, and wherein the control register comprises a delay time field, and wherein the delay time is stored within the delay time field of the control register.

30. The method as recited in claim 29, wherein the configuring step is accomplished by storing the delay time within the delay time filed of the control register, and wherein the storing operation is carried out before the trigger event signal is produced.

31. The method as recited in claim 20, wherein the system clock signal is coupled to the microprocessor model and to the control signal generator.