Non-intrusive software breakpoints in a processor instruction execution pipeline

• US 6,016,555 A
• Filed: 11/19/1997
• Issued: 01/18/2000
• Est. Priority Date: 11/19/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Seshan, Natarajan, Deao, Douglas E.
• Primary Examiner(s): Palys, Joseph E.
• Assistant Examiner(s): OMAR, OMAR B
• Application Number:
  US08/974,744
• Time in Patent Office: 790 Days
• Field of Search: 712/233, 712/237, 712/238, 714/38, 714/1, 714/10, 714/43, 714/46, 714/47, 714/48, 714/35, 714/34, 713/501
• US Class Current: 714/35
• CPC Class Codes: G06F 11/362 Software debugging
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Claims

1. A method for debugging a processor within a data processing system, the processor having an instruction execution pipeline with at least a first pipeline phase followed by a second pipeline phase, comprising the steps of:

forming a software breakpoint instruction within a sequence of instructions by replacing a field within an operational instruction with a predetermined breakpoint code;

fetching and executing a portion of the sequence of instructions in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of overlapping operations in the instruction pipeline;

fetching and partially executing the software breakpoint instruction in the first pipeline phase of the instruction pipeline;

halting the normal operation of the instruction pipeline in response to decoding the breakpoint code in the second pipeline phase of the instruction pipeline;

performing a debug function in response to decoding the breakpoint code; and

restarting the normal operation of the instruction pipeline after the step of performing a debug function without refetching the operational instruction which was replaced by the software breakpoint instruction in a manner such that the operational instruction is executed as if the field within the operational instruction had not been replaced with the predetermined breakpoint code.

2. The method of claim 1, wherein the step of halting further comprises preserving memory access latency by halting the normal operation of the instruction pipeline in a manner that suspends completion of the plurality of overlapping operations.

3. The method of claim 2, wherein the field within the operational instruction is a single bit.

4. The method of claim 2, wherein the field within the operational instruction is not the opcode field.

5. The method of claim 2, further comprising the step of transferring a state representative of the suspended plurality of overlapping states to an external test system.

6. The method of claim 1, wherein the step of restarting further comprises replacing the breakpoint code in the operational instruction after the breakpoint code is decoded in the second phase of the instruction pipeline such that the operational instruction is executed with the original field of the operational instruction.

7. A method for debugging a processor within a data processing system the processor having an instruction execution pipeline with at least a first pipeline phase followed by a second pipeline phase, comprising the steps of:

forming a software breakpoint instruction within a sequence of instructions by replacing a field within an operational instruction with a predetermined breakpoint code, wherein the field within the operational instruction is the opcode field;

fetching and executing a portion of the sequence of instructions in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of overlapping operations in the instruction pipeline;

fetching and partially executing the software breakpoint instruction in the first pipeline phase of the instruction pipeline;

halting the normal operation of the instruction pipeline in response to decoding the breakpoint code in the second pipeline phase of the instruction pipeline in a manner that suspends completion of the plurality of overlapping operations;

performing a debug function in response to decoding the breakpoint code; and

restarting the normal operation of the instruction pipeline after the step of performing a debug function without refetching the operational instruction which was replaced by the software breakpoint instruction; and

wherein the step of restarting further comprises replacing a decoded value of the software breakpoint instruction in a register associated with the second phase of the pipeline with a decoded value representative of the operational instruction which was replaced by the software breakpoint instruction.

8. A method for debugging a processor within a data processing system, the processor having an instruction execution pipeline for executing a sequence of instructions fetched from an instruction memory, comprising the steps of:

selecting a target instruction within the sequence of instructions;

forming a software breakpoint instruction within the sequence of instructions by replacing a selected field within the target instruction with a predetermined breakpoint code;

fetching and executing a portion of the sequence of instructions in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of overlapping operations in the instruction pipeline;

fetching and partially executing the target instruction in the instruction pipeline;

halting the normal operation of the instruction pipeline in response to decoding the breakpoint code in the instruction pipeline;

performing a debug function in the processor in response to decoding the breakpoint code; and

restarting the normal operation of the instruction pipeline after the step of performing a debug function in a manner such that the target instruction is executed as if the selected field within the target instruction had not been replaced with a predetermined breakpoint code without refetching the target instruction from the instruction memory.

9. The method of claim 8, wherein the step of halting further comprises preserving memory access latency by halting the normal operation of the instruction pipeline in a manner that suspends completion of the plurality of overlapping operations.

10. The method of claim 8, wherein the selected field within the target instruction is a single bit.

11. The method of claim 8, wherein the selected field within the target instruction is not the opcode field.

12. The method of claim 8, wherein the step of restarting further comprises the step of replacing the breakpoint code in the target instruction with the original contents of the selected field after the breakpoint code is decoded in the instruction pipeline such that the target instruction is executed with the original selected field of the target instruction without refetching the target instruction from the instruction memory.

13. The method of claim 12, wherein the step of forming a software breakpoint instruction saves the original contents of the selected field of the target instruction in a test system connected to the processor.

14. The method of claim 12, wherein during the step of replacing the breakpoint code the original contents of the selected field of the target instruction is provided by an external test system connected to the processor.

15. A digital system having a processor, the processor comprising:

an instruction register for holding an instruction to be executed;

an instruction execution pipeline connected to the instruction register to execute instructions;

memory circuitry connected to the processor for holding data and instructions;

emulation circuitry connected to the instruction register and to the instruction execution pipeline;

a test port connected to the emulation circuitry for connecting an external test system;

wherein the emulation circuitry comprises detection circuitry operable to detect when a selected field of a target instruction contains a software breakpoint code;

emulation control circuitry operable to halt the normal operation of the instruction execution pipeline in response to the detection circuitry detecting a software breakpoint code so that an external test system connected to the test port can perform a debug operation on the digital system; and

wherein the emulation control circuitry is further operable to restart the normal operation of the instruction pipeline after the detection circuitry detects a software breakpoint code in a manner such that the target instruction is executed as if an original contents of the selected field within the target instruction had not been replaced with the software breakpoint code without refetching the target instruction.

16. The digital system of claim 15, wherein the emulation circuitry further comprises circuitry for replacing the software breakpoint code in the selected field of the target instruction with the original contents of the selected field while the target instruction is in the instruction execution pipeline.

17. The digital system of claim 15, wherein the emulation circuitry further comprises circuitry for replacing decoded results of the software breakpoint code in the selected field of the target instruction with decoded results of the original contents of the selected field while the target instruction is in the instruction execution pipeline.

18. The digital system of claim 15, wherein the selected field within the target instruction is a single bit.

19. The digital system of claim 15, wherein the selected field within the target instruction is not an opcode field.

20. The digital system of claim 15, further comprising at least one peripheral device selected from the group consisting of a timer, a serial port, a disk drive, a ROM and a RAM.