Semiconductor memory, memory device, and memory card
First Claim
1. A semiconductor memory comprising:
- a plurality of memory blocks having a plurality of memory cells;
a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;
control means for controlling the rewriting and reading of data for the memory cells;
storage means for designating defective memory blocks included in said plurality memory blocks; and
detection means for detecting the defective memory blocks designated by said storage means in accordance with a received address signal;
whereinsaid control means inhibits a data rewrite operation for an instruction for a data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.
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Accused Products
Abstract
A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation. The inhibiting function makes it possible to provide a memory device having compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
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Citations
11 Claims
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1. A semiconductor memory comprising:
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a plurality of memory blocks having a plurality of memory cells; a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit; control means for controlling the rewriting and reading of data for the memory cells; storage means for designating defective memory blocks included in said plurality memory blocks; and detection means for detecting the defective memory blocks designated by said storage means in accordance with a received address signal;
whereinsaid control means inhibits a data rewrite operation for an instruction for a data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation. - View Dependent Claims (2, 4)
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3. A semiconductor memory comprising:
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a plurality of memory blocks having a plurality of electrically erasable memory cells; a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit; first control means for controlling the rewriting and reading of data for the memory cells; first storage means for designating defective memory blocks included in said plurality of memory blocks; and detection means for detecting the defective memory blocks designated by the first storage means in accordance with a received address signal;
whereinthe first control means generates a status signal representing the completion of a data rewrite operation for an instruction for a data rewrite operation in such a way that the status can be output to an external unit irrespective of the completion of the data rewrite operation when the detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation. - View Dependent Claims (5, 6, 7)
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8. A semiconductor memory comprising:
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a plurality of memory blocks having a plurality of electrically erasable memory cells; a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit; control means for controlling the rewriting and reading of data for the memory cells; storage means for designating some defective memory blocks included in said plurality of memory blocks; and detection means for detecting the defective memory blocks designated by said storage means in accordance with an address signal;
whereinsaid control means inhibits a data rewrite operation for an instruction for a data rewrite operation when said detection means detects an access to a defective memory block, generates a status signal representing the completion of a data rewrite operation in such a way that the status can be output to an external unit, and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.
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9. A semiconductor memory comprising:
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a plurality of memory blocks having a plurality of memory cells; a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit; control means for controlling the rewriting and reading of data for the memory cells; and storage means which designates defective memory blocks included in said plurality of memory blocks;
whereinsaid control means inhibits a data rewrite operation for an instruction for a data rewrite operation for defective memory blocks designated by said storage means and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.
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10. A semiconductor memory comprising:
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a plurality of electrically erasable memory cells forming two memory blocks, one of which is designated by the least significant bit of an address signal; a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit; control means for controlling the rewriting and reading of data for the memory cells; storage means for designating one of the two memory blocks; and detection means for detecting an access to a defective memory block designated by said storage means in accordance with the least significant bit of an address signal;
whereinsaid control means generates a status signal representing the completion of a data rewrite operation for an instruction for a data rewrite operation in such a way that the status can be output to an external unit irrespective of the completion of the data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.
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11. A semiconductor memory comprising:
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a plurality of electrically erasable memory cells forming two memory blocks, one of which is designated by the most significant bit of an address signal; a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit; control means for controlling the rewriting and reading of data for the memory cells; storage means for designating one of the two memory blocks; and detection means for detecting an access to a defective memory block designated by said storage means in accordance with the most significant bit of an address signal;
whereinsaid control means inhibits a data rewrite operation for an instruction for a data rewrite operation and generates a status signal representing the completion of the data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.
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Specification