Semiconductor memory, memory device, and memory card

• US 6,016,560 A
• Filed: 03/17/1998
• Issued: 01/18/2000
• Est. Priority Date: 06/14/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Okuba, Takao, Wada, Masashi, Furuno, Takeshi
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/981,094
• Time in Patent Office: 672 Days
• Field of Search: 714/718, 714/710, 714/711, 365/195, 365/189.07, 365/189.01, 365/200, 365/201, 395/735
• US Class Current: 714/718
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation. The inhibiting function makes it possible to provide a memory device having compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

Claims

1. A semiconductor memory comprising:

a plurality of memory blocks having a plurality of memory cells;

a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;

control means for controlling the rewriting and reading of data for the memory cells;

storage means for designating defective memory blocks included in said plurality memory blocks; and

detection means for detecting the defective memory blocks designated by said storage means in accordance with a received address signal;

wherein

said control means inhibits a data rewrite operation for an instruction for a data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.

2. A memory device comprising a plurality of semiconductor memories as defined in claim 1, wherein the semiconductor memories are provided in a relation in which one memory is substituted for a defective memory block of another, and external terminals having the same function are connected in common in each semiconductor memory.

4. The semiconductor memory according to claim 2, further including logic means for selectively inverting inputs to be output to a path for supplying address information to said detection means in order to detect an access to a defective memory block designated by the first storage means, and second storage means for holding control information for determining the propriety of the input inverting operation by said logic means.

3. A semiconductor memory comprising:

a plurality of memory blocks having a plurality of electrically erasable memory cells;

a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;

first control means for controlling the rewriting and reading of data for the memory cells;

first storage means for designating defective memory blocks included in said plurality of memory blocks; and

detection means for detecting the defective memory blocks designated by the first storage means in accordance with a received address signal;

wherein

the first control means generates a status signal representing the completion of a data rewrite operation for an instruction for a data rewrite operation in such a way that the status can be output to an external unit irrespective of the completion of the data rewrite operation when the detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.

5. A memory device comprising a plurality of semiconductor memories as defined in claim 3, wherein the semiconductor memories are provided in a relation in which one memory is substituted for a defective memory block of another, and external terminals having the same function are connected in common in each semiconductor memory.

6. A memory card constituted by mounting a plurality of memory devices as defined in claim 5 on a card substrate, wherein

each memory device is provided with an external data input/output terminal, a chip selection terminal, and an address input terminal as external terminals, and

the chip selection terminal is connected to chip selection signal wirings different from each other on a card substrate in each memory device in which the external data input/output terminals are connected to the data wiring of the card substrate in common and external address input terminals of each memory device are connected to the address signal wiring of the card substrate in common.

7. The memory card according to claim 6, further comprising a card controller having one end which is interfaced with the outside of the card substrate and another end which is connected to the data wiring, chip selection wiring, and address signal wiring, and the card controller includes decoding means for decoding part of address information supplied from an external unit to generate the chip selection signal.

8. A semiconductor memory comprising:

a plurality of memory blocks having a plurality of electrically erasable memory cells;

a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;

control means for controlling the rewriting and reading of data for the memory cells;

storage means for designating some defective memory blocks included in said plurality of memory blocks; and

detection means for detecting the defective memory blocks designated by said storage means in accordance with an address signal;

wherein

said control means inhibits a data rewrite operation for an instruction for a data rewrite operation when said detection means detects an access to a defective memory block, generates a status signal representing the completion of a data rewrite operation in such a way that the status can be output to an external unit, and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.

9. A semiconductor memory comprising:

a plurality of memory blocks having a plurality of memory cells;

a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;

control means for controlling the rewriting and reading of data for the memory cells; and

storage means which designates defective memory blocks included in said plurality of memory blocks;

wherein

said control means inhibits a data rewrite operation for an instruction for a data rewrite operation for defective memory blocks designated by said storage means and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.

10. A semiconductor memory comprising:

a plurality of electrically erasable memory cells forming two memory blocks, one of which is designated by the least significant bit of an address signal;

a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;

control means for controlling the rewriting and reading of data for the memory cells;

storage means for designating one of the two memory blocks; and

detection means for detecting an access to a defective memory block designated by said storage means in accordance with the least significant bit of an address signal;

wherein

said control means generates a status signal representing the completion of a data rewrite operation for an instruction for a data rewrite operation in such a way that the status can be output to an external unit irrespective of the completion of the data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.

11. A semiconductor memory comprising:

a plurality of electrically erasable memory cells forming two memory blocks, one of which is designated by the most significant bit of an address signal;

a data input/output buffer for receiving data written in the memory blocks from an external unit and for outputting data read out of the memory blocks to an external unit;

control means for controlling the rewriting and reading of data for the memory cells;

storage means for designating one of the two memory blocks; and

detection means for detecting an access to a defective memory block designated by said storage means in accordance with the most significant bit of an address signal;

wherein

said control means inhibits a data rewrite operation for an instruction for a data rewrite operation and generates a status signal representing the completion of the data rewrite operation when said detection means detects an access to a defective memory block and inhibits a data output operation of said data input/output buffer for an instruction for a data read operation.