Method and apparatus for testing a logic design of a programmable logic device

• US 6,016,563 A
• Filed: 12/30/1997
• Issued: 01/18/2000
• Est. Priority Date: 12/30/1997
• Status: Expired due to Fees

• Current Assignee: Evgeny G. Fleisher
• Original Assignee: Evgeny G. Fleisher
• Inventors: Fleisher, Evgeny G.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Shaw, Brian H.
• Application Number:
  US09/001,109
• Time in Patent Office: 749 Days
• Field of Search: 714/28, 714/27, 714/40, 714/724, 714/725, 395/500.44, 712/227, 324/754, 324/755
• US Class Current: 714/725
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

An apparatus and method are provided for the development, testing and verification of a logic design of a programmable logic device in a real-time user environment to simplify the development of the programmable logic device and associated systems. The apparatus comprises an emulation programmable logic device based on the same family and package of the target programmable logic device. The adapter further comprises a plurality of individually programmable switches for selectively coupling the emulation device to the target device or to a logic device substituting for the target device. The apparatus further comprises a controller, which configures the switches based on control signals received from a host computer system, such that a stimulus applied to the input pins of the target or substitute device are also applied concurrently to the corresponding input pins of the emulation device. The switches are further configured so that the output pins of the emulation device are unloaded from all of their normal functions and are output only as test points. Signal values at internal nodes of the emulation device in response to the stimulus can be traced out via the test points without disturbing the target or substitute device. The apparatus permits dynamic and independent programming and reprogramming of both the target and mirror devices, such that different internal nodes can be traced out quickly and easily. The apparatus may further include an embedded programmable stimulus generator and an embedded logic analyzer.

Claims

1. An apparatus for enabling testing of a logic device, the apparatus comprising:

a first logic device having a plurality of input terminals and a plurality of output terminals;

a plurality of configurable connections coupled to the first logic device to enable configurable coupling of the first logic device to a second logic device, the second logic device having a plurality of input terminals and a plurality of output terminals corresponding to the input terminals and the output terminals of the first logic device; and

a controller configured to control the plurality of switchable connections to couple the input terminals of the first logic device to corresponding input terminals of the second logic device and to decouple the output terminals of the first logic device from corresponding output terminals of the second logic device.

2. An apparatus according to claim 1, wherein the first and second logic devices are programmable logic devices.

3. An apparatus according to claim 2, wherein the first programmable logic device has a device type and a package type that are substantially identical to a device type and a package type of the second programmable logic device.

4. An apparatus according to claim 3, wherein the plurality of configurable connections are programmable to selectively couple particular input or output terminals of the first programmable logic device with corresponding input or output terminals of the second programmable logic device.

5. An apparatus according to claim 1, wherein the controller dynamically reconfigures the configurable connections in responsive to input received from a host processing system.

6. An apparatus for testing a logic design of a target programmable logic device, the apparatus comprising:

a mirror programmable logic device substantially identical to the target programmable logic device, the mirror programmable logic device and the target programmable logic device each having a plurality of input terminals and a plurality of output terminals;

a plurality of switches, each of the switches for connection between a terminal of the mirror programmable logic device and a corresponding terminal of the target programmable logic device; and

a controller for selectively configuring the switches to allow analysis, without affecting any of the output terminals of the target programmable logic device, of an output of the mirror programmable logic device in response to a stimulus applied to the mirror programmable logic device via one of the switches and to the target programmable logic device.

7. An apparatus according to claim 6, wherein the controller is for configuring the switches based on first control inputs received from a host processing system.

8. An apparatus according to claim 6, wherein the controller is further coupled to the mirror programmable logic device for programming the mirror programmable logic device with selected logic designs.

9. An apparatus according to claim 8, wherein the controller is further coupled to the target programmable logic device for programming the target programmable logic device with selected logic designs.

10. An apparatus according to claim 9, wherein the controller is for independently programming both the target programmable logic device and the mirror programmable logic device based on control inputs received from a host processing system.

11. An apparatus according to claim 6, further comprising a clip-on adapter for removably mounting the apparatus to the target programmable logic device to connect the terminals of the target programmable logic device to the switches.

12. An apparatus according to claim 6, further comprising a replacement programmable logic device substantially identical to the target programmable logic device, the replacement programmable logic device for operating as a substitute for the target programmable logic device for purposes of said testing.

13. An apparatus according to claim 6, wherein when the target programmable logic device is mounted to a target board, the switches are configurable to allow programming of the logic design of the target programmable logic device from either the apparatus or from the target board.

14. An apparatus according to claim 6, further comprising a programmable pattern generator coupled to the controller for generating the stimulus.

15. An apparatus for allowing testing of a logic design of a target programmable logic device, the apparatus comprising:

a mirror programmable logic device substantially identical to the target programmable logic device for emulating the target programmable logic device, the mirror programmable logic device and the target programmable logic device each having a plurality of input/output terminals;

a programmable switch module including a plurality of individually configurable switches, each of the plurality of individually configurable switches for connection between an input or output input terminal of the mirror programmable logic device and a corresponding input or output terminal of the target programmable logic device; and

a controller coupled to the switch module for selectively configuring the switches based on first control input to allow detection, at the output terminals of the mirror programmable logic device, of responses of the mirror programmable logic device to a stimulus applied concurrently to both the mirror programmable logic device and the target programmable logic device, while preventing the responses of the mirror programmable logic device from being received at output terminals of the target programmable logic device.

16. An apparatus according to claim 15, wherein the controller is further coupled to the mirror programmable logic device for programming the mirror programmable logic device with selected logic designs.

17. An apparatus according to claim 16, wherein the controller is further coupled to the target programmable logic device for programming the target programmable logic device with selected logic designs.

18. An apparatus according to claim 17, wherein the controller is for independently programming both the target programmable logic device and the mirror programmable logic device based on control inputs received from a host processing system.

19. An apparatus according to claim 15, wherein the apparatus further comprises an adapter for removably mounting the apparatus to the target programmable logic device to connect the terminals of the target programmable logic device to the switches.

20. An apparatus according to claim 15, further comprising a replacement programmable logic device substantially identical to the target programmable logic device, the replacement programmable logic device for operating as a substitute for the target programmable logic device during said testing.

21. An apparatus according to claim 15, further comprising a programmable pattern generator coupled to the controller for generating the stimulus.

22. An apparatus for allowing testing of a target programmable logic device programmable logic device, the apparatus comprising:

a mirror programmable logic device from substantially the same device family and of substantially the same device type as the target programmable logic device, the mirror programmable logic device and the target programmable logic device each having a plurality of input/output terminals;

a programmable switch module including a plurality of individually configurable switches, each of the plurality of individually configurable switches for connection between an input or output input terminal of the mirror programmable logic device and a corresponding input or output terminal of the target programmable logic device; and

a controller coupled to the switch module for selectively configuring the switches based on first control input to couple input terminals of the mirror programmable logic device with the corresponding input terminals of the target programmable logic device and to decouple output terminals of the mirror programmable logic device from the corresponding output terminals of the target programmable logic device, such that a stimulus applied to an input terminal of the target programmable logic device is applied via the switching module to the corresponding input terminal of the mirror programmable logic device, and such that responses of the mirror programmable logic device to the stimulus are detectable at the output terminals of the mirror programmable logic device, wherein the controller is further coupled to the mirror programmable logic device for programming the mirror programmable logic device with selected logic designs based on second control input.

23. An apparatus according to claim 22, further comprising a clip-on adapter for removably mounting the apparatus to the target programmable logic device to connect the input/output terminals of the target programmable logic device to the switches.

24. An apparatus according to claim 22, further comprising a replacement programmable logic device substantially identical to the target programmable logic device, the replacement programmable logic device for operating in substitution for the target programmable logic device.

25. An apparatus according to claim 22, wherein the first and second control inputs are received from a host processing system, such that the logic designs of both the target programmable logic device and the mirror programmable logic device can be dynamically and independently configured from the host processing system.

26. An apparatus according to claim 22, wherein the target programmable logic device is mounted to a target board, and wherein the switches are configurable to allow programming of the logic design of the target programmable logic device from either the apparatus or from the target board.

27. An apparatus according to claim 22, further comprising a programmable pattern generator coupled to the controller for generating the stimulus.

28. A method of allowing testing of a logic design of a target programmable logic device, the method comprising:

operating a mirror programmable logic device substantially identical to the target programmable logic device, the mirror programmable logic device and the target programmable logic device each having a plurality of terminals; and

selectively configuring a plurality of connections, each of the connections for selectively connecting a terminal of the mirror programmable logic device to a corresponding terminal of the target programmable logic device, said selectively configuring including configuring the plurality of connections to allow detection of an output of the mirror programmable logic device in response to a stimulus applied concurrently to inputs of both the mirror programmable logic device and the target programmable logic device while preventing outputs of the mirror programmable logic device from affecting the target programmable logic device.

29. A method according to claim 28, further comprising:

receiving control input from a host processing system; and

automatically reconfiguring the set of connections in response to the control input.

30. A method according to claim 28, further comprising:

receiving first control input from a host processing system; and

automatically programming a logic design of one of the target programmable logic device and the mirror programmable logic device in response to the first control input.

31. A method of testing a logic design of a programmable logic device, the method comprising:

configuring a set of connections between a first programmable logic device and a second programmable logic device to enable an input signal applied to an input terminal of one of the first programmable logic device and the second programmable logic device to also be applied concurrently to a corresponding input terminal of the other of the first programmable logic device and the second programmable logic device, while decoupling an output terminal of the first programmable logic device from the second programmable logic device;

applying the input signal concurrently to the corresponding input terminals of the first and second programmable logic devices; and

outputting at a test terminal a signal from the output terminal of the first programmable logic device in response to the input signal.

32. A method according to claim 31, wherein the first programmable logic device is substantially identical to the second programmable logic device and is for emulating the second programmable logic device.

33. A method according to claim 31, further comprising:

receiving control input from a host processing system; and

automatically reconfiguring the set of connections in response to the control input.

34. A method according to claim 31, further comprising:

receiving first control input from a host processing system; and

automatically programming a logic design of the first programmable logic device in response to the first control input.

35. A method according to claim 31, further comprising:

receiving second control input from the host processing system; and

automatically programming a logic design of the second programmable logic device in response to the second control input.