Lithographic mask and method for fabrication thereof

• US 6,017,658 A
• Filed: 05/13/1992
• Issued: 01/25/2000
• Est. Priority Date: 05/13/1992
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Dobisz, Elizabeth A., Rhee, Kee W., Peckerar, Martin C., Marrian, Christie R. K.
• Primary Examiner(s): CHAPMAN, MARK A
• Application Number:
  US07/882,226
• Time in Patent Office: 2,813 Days
• Field of Search: 430/5, 250/492.2
• US Class Current: 430/5
• CPC Class Codes: G03F 1/22 Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
• CPC Class Codes: G03F 1/78 by charged particle beam [CPB], e.g. electron beam patterning of masks
• CPC Class Codes: G03F 7/2061 Electron scattering (proximity) correction or prevention methods
• CPC Class Codes: H01J 2237/31794 affecting masks

Abstract

Improvement in resolution in terms of minimum feature sizes and proximity fects in an electronic mask is attained by making the mask using a high voltage electron beam which deflects or blocks backscattered electrons. The novel mask structure comprises a transparent support, an absorber layer disposed on said support, a dielectric layer disposed on said absorber layer, and a resist layer disposed on said dielectric layer. It is the dielectric layer which is credited for improving resolution in said mask which can be used a multiple number of times in printing a pattern for various applications, including electronic devices and integrated circuits.

Claims

1. In a method for making an electronic mask using a high voltage electron beam, which mask comprises a support medium, an absorber layer disposed above said support medium, and a resist layer disposed above said absorber layer, the improvement comprising the step of providing a dielectric layer between said absorber layer and said resist layer, said dielectric layer having the function of preventing at least some electrons from reentering said resist layer.

2. Method of claim 1 including the step of directing high voltage electrons from an electron beam operating at 1 to 500 kiloelectron volts at said resist layer.

3. Method of claim 2 wherein the electron beam operates at about 10 to 100 kiloelectron volts, the dielectric layer is about 1 to about 1000 nm thick and said support is selected from thin and thick supports, said thin supports are about 0.01 to about 10 um thick and are selected from silicon carbide, silicon nitride, boron nitride, diamond, carbon, and silicon, and said thick supports are about 1 to about 1500 um thick and are selected from glasses and quartz.

4. Method of claim 3 wherein said absorber is selected from chromium, ferric oxide, tungsten, and gold and thickness thereof is about 30 to 1000 nm.

5. Method of claim 4 wherein said dielectric layer is about 10 to 400 nm thick and is selected from the group consisting of silicon nitrides and wherein said resist layer is selected from the group consisting of negative resists which is about 10 to 1000 nm thick.

6. In a method for making an electronic mask using an electron beam rated at about 10 to 100 kiloelectron volts, said mask comprising a support transparent to x-rays selected from silicon carbide, silicon nitride, biron nitride, diamond, silicon, and carbon;

an absorber layer disposed on said support selected from tungsten and gold; and

a negative resist disposed on said absorber layer selected from chemically amplified novolac resists;

the improvement in the method for making said mask comprising the steps of providing a dielectric layer between said absorber layer and said resist layer about 1 to about 1000 nm thick, said dielectric layer having the function of reducing proximity effects in the pattern written with said electron beam on said resist.

7. Method of claim 6 wherein said support is about 0.01 to about 10 μ

m thick;

said absorber layer is about 1 to about 1500 nm thick;

said dielectric layer is selected from the group consisting of silicon nitrides and is about 1 to about 500 nm thick; and

said resist layer is about 10 to 1000 nm thick.

8. Method of claim 6 wherein said support is about 0.1 to 5 um thick;

said absorber layer is about 30 to 1000 nm thick, said dielectric layer is about 10 to 400 nm thick, and said resist layer is a negative resist of about 10 to 1000 nm thick;

said method also including the step of depositing up to two stop etch layers.