Method and system for yield loss analysis by yield management system
First Claim
1. A method for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages, said method comprising the steps of:
- inspecting semiconductor devices on said wafer visually to identify the location of visual defects on dies being manufactured on said wafer and to maintain a count of visual defects on said dies by location,inspecting said semiconductor dies on said wafer to determine the location and number defective dies on said wafer at each of said manufacturing stages,calculating the defective die count for each stage for said wafer,calculating the defective bad die count for each stage for said wafer,determining the percentage of the defective bad die count divided by the defective die count,plotting the trend of the percentage of yield loss and the percentage of defective bad dies for each of said manufacturing stages, andcomparing said plots to determine said killer stage from analysis of the relative trends of matching between said plots of yield lost and the percentage of bad dies for said stage.
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Abstract
A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.
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Citations
6 Claims
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1. A method for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages, said method comprising the steps of:
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inspecting semiconductor devices on said wafer visually to identify the location of visual defects on dies being manufactured on said wafer and to maintain a count of visual defects on said dies by location, inspecting said semiconductor dies on said wafer to determine the location and number defective dies on said wafer at each of said manufacturing stages, calculating the defective die count for each stage for said wafer, calculating the defective bad die count for each stage for said wafer, determining the percentage of the defective bad die count divided by the defective die count, plotting the trend of the percentage of yield loss and the percentage of defective bad dies for each of said manufacturing stages, and comparing said plots to determine said killer stage from analysis of the relative trends of matching between said plots of yield lost and the percentage of bad dies for said stage. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification
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- Resources
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsChang, Wen-Chen, Chang, Chao-Hsin, Yang, Jiunn-Der, Yeh, Renn-Shyan
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Primary Examiner(s)CHAUDHARI, CHANDRA P
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Application NumberUS09/067,264Time in Patent Office638 DaysField of Search438/7, 438/10, 438/11, 438/12, 438/16, 438/17, 438/18US Class Current438/7CPC Class CodesH01L 22/12 for structural parameters, ...H01L 22/20 Sequence of activities cons...
