Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties

• US 6,018,179 A
• Filed: 11/05/1998
• Issued: 01/25/2000
• Est. Priority Date: 11/05/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Gardner, Mark I., Hause, Fred N., Wristers, Derick J.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US09/187,028
• Time in Patent Office: 446 Days
• Field of Search: 257/408, 257/210, 257/211, 257/412, 257/413, 257/900, 257/344, 257/336
• US Class Current: 257/336
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed. The slope etched void is then filled with a gate conductor and the surface is planarized in a CMP process. The gate conductor then has a shape wherein its lower surface is smaller than its upper surface. Then, the substrate is isotropically etched to remove portions of the oxide layer and nitride layer unprotected by the gate conductor. The remaining structure includes integrally formed spacers. Active regions, LDD regions and punchthrough regions are then formed to complete formation of the transistor.

Claims

1. A transistor formed on a semiconductor substrate, the transistor comprising:

a source formed in the semiconductive substrate;

a drain formed in the semiconductive substrate;

a channel defined in the semiconductive substrate between the source and the drain;

a gate dielectric residing above the channel; and

a gate conductor residing upon the gate dielectric, the gate conductor having an upper surface, a lower surface, and sloped sidewalls, the lower surface residing upon the gate dielectric, the upper surface having a larger area than the lower surface such that the length of the channel is less than a corresponding length of the upper surface of the gate conductor, wherein a cross-sectional shape of the gate conductor corresponds to a cross-sectional shape of a slope etched void that was formed in an oxide layer that was deposited and slope etched to form the slope etched void.

2. The transistor of claim 1, wherein the gate dielectric comprises an oxide layer portion that was formed from the oxide layer.

3. The transistor of claim 1, wherein the gate dielectric comprises:

a nitride layer portion that was deposited upon the semiconductive substrate; and

an oxide layer portion that resides upon the nitride layer portion and that was formed from the oxide layer.

4. The transistor of claim 1, further comprising:

a well;

a voltage threshold region;

a lightly doped drain region; and

a punchthrough region.

5. The transistor of claim 1, further comprising tapered spacers residing adjacent the gate conductor, wherein the tapered spacers were formed from the oxide layer and correspond to the cross-sectional shape of the slope etched void.

6. The transistor of claim 1, further comprising:

a dielectric layer formed adjacent the sidewalls and the lower surface of the gate conductor that corresponds to the shape of the slope etched void.

7. The transistor of claim 1, wherein:

the gate dielectric comprises a portion of a nitride layer portion that was deposited; and

the gate conductor resides upon the portion of the nitride layer.

8. A transistor formed on a semiconductor substrate, the transistor comprising:

a source formed in the semiconductive substrate;

a drain formed in the semiconductive substrate;

a channel defined in the semiconductive substrate between the source and the drain;

a gate dielectric residing above the channel;

a gate conductor residing upon the gate dielectric, the gate conductor having an upper surface, a lower surface, and sloped sidewalls, the lower surface residing upon the gate dielectric, the upper surface having a larger area than the lower surface such that the length of the channel is less than a corresponding length of the upper surface of the gate conductor, wherein a cross-sectional shape of the gate conductor corresponds to a cross-sectional shape of a slope etched void that was formed in an oxide layer that was deposited and slope etched to form the slope etched void; and

wherein the gate dielectric comprises an insulative film that resides upon the channel and that also resides adjacent the sloped sidewalls of the gate conductor.

9. The transistor of claim 8, wherein the gate dielectric further comprises a nitride layer portion that resides upon the semiconductive substrate.

10. The transistor of claim 8, further comprising tapered spacers residing adjacent the gate conductor that were formed from the oxide layer.

11. The transistor of claim 8, further comprising:

a well;

a voltage threshold region;

a lightly doped drain region; and

a punchthrough region.

12. The transistor of claim 8, further comprising tapered spacers residing adjacent the gate conductor.