Programmable integrated circuit having parallel routing conductors coupled to programming drivers in different locations

• US 6,018,251 A
• Filed: 09/17/1997
• Issued: 01/25/2000
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Kolze, Paige A.
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/931,896
• Time in Patent Office: 860 Days
• Field of Search: 326/37-41
• US Class Current: 326/41
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable integrated circuit (see FIG. 18) includes a plurality of interface cells with programmable antifuses disposed on a branch of a routing conductor. The routing conductor extends in a first direction and is coupled to one terminal of a programming transistor. The other terminal of the programming transistor is coupled to a programming driver via a programming conductor that extends in the first direction. The branch of the routing conductor crosses a plurality of routing wire segments of one of the interface cells, where programmable antifuses are disposed to couple the branch of the routing conductor to one or more of the routing wire segments. The routing wire segments extend parallel to one another in the first direction and are each coupled to a first terminal of separate programming transistors. The second terminals of the programming transistors are coupled to programming drivers via programming conductors that extend in a second direction, which is perpendicular to the first direction. Thus, the programming drivers for the routing wire segments and the routing conductor are positioned in different locations. Accordingly, when an antifuse is programming to couple the branch of the routing conductor with one of the routing wire segments, the two programming drivers are controlled by two different programming control shift registers.

Claims

1. A field programmable integrated circuit, comprising:

a plurality of logic modules disposed in an array having rows and columns, each column extending in a first dimension;

a first routing conductor extending in the first dimension between two adjacent columns of logic modules;

a first programming transistor having a first electrode, a second electrode and a control electrode, the first electrode being coupled to the first routing conductor;

a first programming driver;

a first programming conductor extending in a second dimension perpendicular to said first dimension, the first programming conductor extending from the first programming driver, past multiple columns of logic modules, and to the second electrode of the first programming transistor;

a plurality of interface cells disposed in a column extending in the first dimension;

a second routing conductor extending in the first dimension between the column of interface cells and the array of logic modules, the second routing conductor having a branch that extends in the second dimension, the branch crossing a plurality of routing wire segments of one of the interface cells, the routing wire segments of the interface cell extending parallel to one another in the first dimension, the interface cell having a plurality of antifuses disposed to programmably couple a selected one or ones of the routing wire segments to the branch of the second routing conductor;

a second programming transistor having a first electrode, a second electrode and a control electrode, the first electrode of the second programming transistor being coupled to the second routing conductor;

a second programming driver; and

a second programming conductor extending in the first dimension from the second programming driver to the second electrode of the second programming transistor.

2. The field programmable integrated circuit of claim 1, wherein the first programming driver is disposed adjacent a first side of the field programmable integrated circuit and wherein the second programming driver is disposed adjacent a second side of the field programmable integrated circuit, the first and second sides forming a corner of the field programmable integrated circuit.

3. The field programmable integrated circuit of claim 1, wherein the first and second routing conductors are directly connected together.

4. The field programmable integrated circuit of claim 1, further comprising:

a third routing conductor extending in the second dimension, the first and second routing conductors, being coupled via clock buffers to the third routing conductor.

5. The field programmable integrated circuit of claim 1, further comprising:

a terminal which is coupled to the first and second routing conductors such that a signal on the terminal can pass onto the first and second routing conductors without passing through any antifuse.

6. The field programmable integrated circuit of claim 5, wherein the first and second routing conductors are coupled to the terminal via an input buffer.

7. The field programmable integrated circuit of claim 1, wherein a dedicated input terminal that cannot be used as an output terminal is coupled to the first and second routing conductors.