High-speed clock-enabled latch circuit

• US 6,018,260 A
• Filed: 08/06/1997
• Issued: 01/25/2000
• Est. Priority Date: 08/06/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Gabara, Thaddeus John
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/906,784
• Time in Patent Office: 902 Days
• Field of Search: 327/200, 327/199, 327/201, 327/202, 327/203, 327/208-212, 327/218, 327/51-55, 327/57
• US Class Current: 327/201
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A novel latch circuit configuration that substantially reduces inverter-based setup and hold times. The latch circuit includes first and second input switches connected to an effective sense amplifier configuration. It is possible for the input switches to receive complementary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.

Claims

1. A latch circuit comprising:

first and second transistors coupled to each other at a first junction and in series between a first voltage source and a controllable enable switch coupled to a second voltage source, a gate of said second transistor coupled to a first controllable input switch receiving a first input signal;

third and fourth transistors coupled to each other at a second junction and in series between the first voltage source and the controllable enable switch, a gate of said fourth transistor coupled to a second controllable input switch receiving a corresponding second input signal, gates of said first and third transistors coupled to said second and first junctions, respectively; and

a controllable initialization switch coupled between the first and second junctions, the switches being controllable by a clock signal, wherein when the clock signal is at a first signal level, said controllable enable switch electrically connects the second and fourth transistors to the second voltage source and wherein when the clock signal is at a second signal level, the first and second controllable input switches provide the input signals to the gates of the second and fourth transistors and the controllable initialization switch electrically connects the first and second junctions.

2. The circuit of claim 1 further comprising first and second resistive elements coupled between the respective first and second junctions and the second voltage source.

3. The circuit of claim 2 wherein the resistive elements are implemented using transistors.

4. The circuit of claim 1 for receiving a balanced input signal comprising the first and second input signals, wherein said second input signal received at said second controllable input switch is a complementary signal to the first input signal received at said first controllable input switch.

5. The circuit of claim 1, wherein at least one of the first and second junctions is biased during an initialization mode to a signal level having a magnitude between magnitudes of said first and second voltage sources.

6. The circuit of claim 5 wherein the signal level magnitude is approximately at a midpoint between the magnitudes of said first and second voltage sources.

7. The circuit of claim 1 further comprising first and second cross-coupling controllable switches coupled between said respective first and second junctions and respective gates of said fourth and second transistors, wherein said cross-coupling switches are controllable by the clock signal such that when said clock signal is at the first signal level, the first and second junctions are electrically connected to the gates of said fourth and second transistors, respectively.

8. The circuit of claim 1 wherein at least one of said controllable enable switch and said first and second controllable input switches comprises a transistor.

9. The circuit of claim 1 wherein at least one of said controllable enable switch and said first and second controllable input switches comprises a transmission gate circuit.

10. An integrated circuit device comprising the latch circuit of claim 1.

11. A flip-flop comprising the latch circuit of claim 1 and a static latch, said static latch having a signal input coupled to at least one of said first and second junctions of the latch circuit of claim 1.

12. The flip-flop of claim 11 further comprising first and second resistive elements coupled between the respective first and second junctions and the second voltage source.

13. The flip-flop of claim 11 further comprising first and second cross-coupling controllable switches coupled between said respective first and second junctions and respective gates of said fourth and second transistors, wherein said cross-coupling switches are controllable by the clock signal such that when said clock signal is at the first signal level, the first and second junctions are electrically connected to the gates of said fourth and second transistors, respectively.

14. The flip-flop of claim 11, wherein said signal input of said static latch comprises balanced signal inputs of said static latch, and said balanced signal inputs are coupled to said latch circuit first and second junctions.

15. The flip-flop of claim 14, wherein said static latch further comprises:

first and second inverters;

a first pair of controllable switches coupled between said respective latch circuit first and second junctions and said first and second inverters; and

a second pair of controllable switches cross-coupled between said first pair of controllable switches and outputs of said inverters, respectively.