CMOS differential amplifier for a delta sigma modulator applicable for an analog-to-digital converter

• US 6,018,262 A
• Filed: 04/27/1998
• Issued: 01/25/2000
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Maejima, Toshio, Yamamoto, Yusuke, Noro, Masao
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/067,046
• Time in Patent Office: 638 Days
• Field of Search: 327/309, 327/323, 327/327, 327/328, 327/561, 327/562, 327/563, 330/252, 330/260, 330/291, 330/293
• US Class Current: 327/328
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/444 using non-linear elements, e.g. limiters

Abstract

An analog-digital converter includes a ΔΣ modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the ΔΣ modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The ΔΣ modulator includes at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.

Claims

1. A CMOS differential amplifier comprising:

a CMOS operational amplifier; and

at least one amplitude-limiting circuit connected between an input terminal and an output terminal of said CMOS operational amplifier, wherein said at least one amplitude-limiting circuit comprises first and second PMOS transistors and first and second NMOS transistors, wherein said first PMOS transistor and said first NMOS transistor are connected in parallel to said second PMOS transistor and said second NMOS transistor,

wherein said first PMOS transistor and said first NMOS transistor each further comprise a drain, a source, and gate,

wherein said the source of said first PMOS transistor and the drain of said first NMOS transistor are commonly connected to the input terminal of said CMOS operational amplifier and the gates of both of said first PMOS transistor and said first NMOS transistor are commonly connected to the input terminal of said CMOS operational amplifier,

wherein said second PMOS transistor and said second NMOS transistor each further comprise a drain, a source, and gate, and

wherein said the source of said second PMOS transistor and the drain of said second NMOS transistor are commonly connected to the output terminal of said CMOS operational amplifier and the gates of both of said second PMOS transistor and said second NMOS transistor are commonly connected to the output terminal of said CMOS operational amplifier.

2. The CMOS differential amplifier of claim 1, further comprising at least one resistor connected between said input terminal and said output terminal of said CMOS operational amplifier.

3. The CMOS differential amplifier of claim 1, further comprising at least one capacitor connected between said input terminal and said output terminal of said CMOS operational amplifier.

4. The CMOS differential amplifier of claim 1, wherein said at least one amplitude-limiting circuit limits an output amplitude of said CMOS operational amplifier thereby stabilizing an operating point of said CMOS operational amplifier, said CMOS differential amplifier comprising part of a switched-capacitor integrator in a delta sigma modulator for an analog-to-digital converter.

5. The CMOS differential amplifier of claim 1, wherein said CMOS operational amplifier is configured as a single-end output type CMOS differential amplifier.

6. The CMOS differential amplifier of claim 1, wherein said CMOS operational amplifier is configured as a double-end type CMOS differential amplifier and wherein said at least one amplitude-limiting circuit further comprises a first amplitude-limiting circuit connected between a non-inverting input and a first output and a second amplitude-limiting circuit connected between an inverting input and a second output.

7. A CMOS differential amplifier comprising:

a CMOS operational amplifier; and

at least one amplitude-limiting circuit connected between an input terminal and an output terminal of said CMOS operational amplifier, wherein said at least one amplitude-limiting circuit comprises a first PMOS transistor and a second PMOS transistor and a first NMOS transistor and a second NMOS transistor, wherein said first PMOS transistor and said first NMOS transistor are connected in parallel to said second PMOS transistor and said second NMOS transistor,

wherein said first and second PMOS transistors and said first and second NMOS transistors have optimum gate width-to-gate length ratios in order to provide a stable operating point for said CMOS differential amplifier

wherein said first PMOS transistor and said first NMOS transistor each further comprise a drain, a source, and gate,

wherein said the source of said first PMOS transistor and the drain of said first NMOS transistor are commonly connected to the input terminal of said CMOS operational amplifier and the gates both of said first PMOS transistor and said first NMOS transistor are commonly connected to the input terminal of said CMOS operational amplifier,

wherein said second PMOS transistor and said second NMOS transistor each further comprise a drain, a source, and gate, and

wherein said the source of said second PMOS transistor and the drain of said second NMOS transistor are commonly connected to the output terminal of said CMOS operational amplifier and the gates both of said second PMOS transistor and said second NMOS transistor are commonly connected to the output terminal of said CMOS operational amplifier.

8. The CMOS differential amplifier of claim 7, further comprising at least one resistor connected between said input terminal and said output terminal of said CMOS operational amplifier.

9. The CMOS differential amplifier of claim 7, further comprising at least one capacitor connected between said input terminal and said output terminal of said CMOS operational amplifier.

10. The CMOS differential amplifier of claim 7, wherein said CMOS differential amplifier comprises part of a switched-capacitor integrator in a delta sigma modulator for an analog-to-digital converter.

11. The CMOS differential amplifier of claim 7, wherein said CMOS operational amplifier is configured as a single-end output type CMOS differential amplifier.

12. The CMOS differential amplifier of claim 7, wherein said CMOS operational amplifier is configured as a double-end type CMOS differential amplifier and wherein said at least one amplitude-limiting circuit further comprises a first amplitude-limiting circuit connected between a non-inverting input and a first output and a second amplitude-limiting circuit connected between an inverting input and a second output.

13. The CMOS differential amplifier of claim 7, further comprising a first resistor connected between a first input and a non-inverting input of said CMOS operational amplifier and a second resistor connected between a second input and an inverting input of said CMOS operational amplifier.