Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability
First Claim
1. A method for modulating a predefined number of bits of a binary data word Xn with a predetermined set of target constraints into codewords having a predefined number of code bits Cn+1 bits comprising the steps of:
- a. pad the data word [Xn =x1 x2 . . . xn ] with zeros to the form [0 x1 x2 . . . xn 0],b. process the padded data word with 1⊕
D to form the pre-encoded codeword C'"'"'n+1 such that all C'"'"'n+1 have even weight; and
c. choose the pre-encoded codewords C'"'"'n+1 which violate a target constraint and invert in a decodable way an odd number of bits of the codeword to form the odd parity codeword Cn+1 which satisfies the target constraints.
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Abstract
Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n≧5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.
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Citations
24 Claims
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1. A method for modulating a predefined number of bits of a binary data word Xn with a predetermined set of target constraints into codewords having a predefined number of code bits Cn+1 bits comprising the steps of:
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a. pad the data word [Xn =x1 x2 . . . xn ] with zeros to the form [0 x1 x2 . . . xn 0], b. process the padded data word with 1⊕
D to form the pre-encoded codeword C'"'"'n+1 such that all C'"'"'n+1 have even weight; andc. choose the pre-encoded codewords C'"'"'n+1 which violate a target constraint and invert in a decodable way an odd number of bits of the codeword to form the odd parity codeword Cn+1 which satisfies the target constraints. - View Dependent Claims (2, 3, 4)
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5. A method for RLL coding a predefined number of bits of a binary data word Xn with predetermined target constraints into codewords having a predefined number of code bits Cn+1 comprising the steps of:
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a. pad the data word Xn =[x1 x2 . . . xn ] with zeros to the form [0 x1 x2 . . . xn 0], b. process the padded data word with 1⊕
D to form the pre-encoded codeword C'"'"'n+1 ; andc. choose the pre-encoded codewords which violate a target constraint and invert an odd number of bits of the codeword to form the codeword Cn+1 so that said target constraints are satisfied. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer hard disk drive having a digital communications system which modulates a predefined number of bits of a binary data word Xn with a predetermined set of target constraints into codewords having a predefined number of code bits Cn+1 bits comprising:
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a. a convolution circuit for processing the padded data word of the form [0 Xn 0], with 1⊕
D to form the pre-encoded codeword C'"'"'n+1 ; andb. a inversion circuit which inverts an odd number of bits of the any codewords which violate a target constraint to form the codeword Cn+1. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification