Method and apparatus for high-rate n/n+1 low-complexity modulation codes with adjustable codeword length and error control capability

• US 6,018,304 A
• Filed: 03/23/1998
• Issued: 01/25/2000
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bessios, Anthony
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US09/046,347
• Time in Patent Office: 673 Days
• Field of Search: 341/58, 341/59, 341/100, 341/73, 714/761, 714/800, 714/799, 714/754, 714/812, 714/802, 714/811, 708/628
• US Class Current: 341/58
• CPC Class Codes: H03M 7/46 Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind

Abstract

Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n≧5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.

Claims

1. A method for modulating a predefined number of bits of a binary data word X_n with a predetermined set of target constraints into codewords having a predefined number of code bits C_n+1 bits comprising the steps of:

a. pad the data word [X_n =x₁ x₂ . . . x_n ] with zeros to the form [0 x₁ x₂ . . . x_n 0],

b. process the padded data word with 1⊕

D to form the pre-encoded codeword C'"'"'_n+1 such that all C'"'"'_n+1 have even weight; and

c. choose the pre-encoded codewords C'"'"'_n+1 which violate a target constraint and invert in a decodable way an odd number of bits of the codeword to form the odd parity codeword C_n+1 which satisfies the target constraints.

2. The modulation method according to claim 1, further comprising the decoding steps of:

d. Receiving a codeword Y_n+1 ;

e. Checking the parity of codeword Y_n+1 to determine odd parity and even parity words of the received codewords, for codewords Y_n+1 found to have even parity skip to step g, otherwise proceeding to step f;

f. inverting back to the initial even weight state by reversing the chosen odd number of bits of received odd weight codewords Y_n+1 ; and

g. Process the evenweight codewords resulting from step f and the received even weight parity codewords Y_n+1 from step e with 1/(1⊕

D) to restore the n bit data word X_n.

3. The modulation method according to claim 2, further comprising:

h. detecting illegal codewords which were mapped out of the valid set of code words by the inverting of bits in step b and passing an error condition signal to an error correction system.

4. The modulation method according to claim 2, wherein step c further comprises the codeword C_n+1 being stored on a computer hard disk drive and wherein step d further comprises receiving the codeword Y_n+1 from said computer hard disk drive.

5. A method for RLL coding a predefined number of bits of a binary data word X_n with predetermined target constraints into codewords having a predefined number of code bits C_n+1 comprising the steps of:

a. pad the data word X_n =[x₁ x₂ . . . x_n ] with zeros to the form [0 x₁ x₂ . . . x_n 0],

b. process the padded data word with 1⊕

D to form the pre-encoded codeword C'"'"'_n+1 ; and

c. choose the pre-encoded codewords which violate a target constraint and invert an odd number of bits of the codeword to form the codeword C_n+1 so that said target constraints are satisfied.

6. The modulation method according to claim 5, further comprising the decoding steps of:

d. Receiving a codeword Y_n+1 ;

e. Checking the parity of codeword Y_n+1 to find odd parity and even parity words of the received codewords Y_n+1, for codewords Y_n+1 found to have even parity skip to step g, otherwise proceeding to step f;

f. inverting back to the initial even weight state by reversing the chosen odd number of bits of received odd weight codewords Y_n+1 ; and

g. Process the evenweight codewords resulting from step f and the received even weight parity codewords Y_n+1 from step e with 1/(1⊕

D) to restore the n bit data word X_n.

7. The modulation method according to claim 6, further comprising:

h. detecting illegal codewords which were mapped out of the valid set of code words by the inverting of bits in step b and passing an error condition signal to an error correction system.

8. The modulation method according to claim 6, wherein step c further comprises the codeword C_n+1 being stored on a computer hard disk drive and wherein step d further comprises receiving the codeword Y_n+1 from said computer hard disk drive.

9. The modulation method according to claim 6, wherein the code rate and constraints is of the type 24/25(d=0, k=12) with a 2-bit partition of the pre-encoded codeword.

10. The modulation method according to claim 6, wherein the code rate and constraints is of the type 16/17(d=0, k=8) with a 2-bit partition of the pre-encoded codeword.

11. The modulation method according to claim 6, wherein the code rate and constraints is of the type 8/9(d=0, k=4) with a 2-bit partition of the pre-encoded codeword.

12. The modulation method according to claim 6, wherein the code rate and constraints is of the type 32/33(d=0, k=16) with a 2-bit partition of the pre-encoded codeword.

13. The modulation method according to claim 6, wherein the code rate and constraints is of the type 24/25(d=0, k=12) with a 5-bit partition of the pre-encoded codeword.

14. The modulation method according to claim 6, wherein the code rate and constraints is of the type 16/17(d=0, k=8) with a 5-bit partition of the pre-encoded codeword.

15. The modulation method according to claim 6, wherein the code rate and constraints is of the type 32/33(d=0, k=16) with a 5-bit partition of the pre-encoded codeword.

16. The modulation method according to claim 6, wherein the code rate and constraints is of the type 8/9(d=0, k=7) with a 1-bit partition of the pre-encoded codeword.

17. A computer hard disk drive having a digital communications system which modulates a predefined number of bits of a binary data word X_n with a predetermined set of target constraints into codewords having a predefined number of code bits C_n+1 bits comprising:

a. a convolution circuit for processing the padded data word of the form [0 X_n 0], with 1⊕

D to form the pre-encoded codeword C'"'"'_n+1 ; and

b. a inversion circuit which inverts an odd number of bits of the any codewords which violate a target constraint to form the codeword C_n+1.

18. The computer hard disk drive according to claim 17, further comprising:

c. a parity circuit for checking the parity of the received codeword Y_n+1 to find odd parity and even parity words of the received codewords Y_n+1 ;

d. a inverting circuit for inverting back to the initial state by reversing the chosen odd number of bits of all odd parity words; and

e. a deconvolution circuit for processing the inverted odd parity codewords and the even parity codewords with 1/(1⊕

D) to restore the n bit data word X_n.

19. The computer hard disk drive according to claim 18, wherein the code rate and constraints is of the type 24/25(d=0, k=12), a 2-bit partition of the pre-encoded codeword is formed and the maximum number of bits flipped in a single codeword is three.

20. The computer hard disk drive according to claim 18, wherein the code rate and constraints is of the type 16/17(d=0, k=8), a 2-bit partition of the pre-encoded codeword is formed and the maximum number of bits flipped simultaneously in a single codeword is three.

21. The computer hard disk drive according to claim 18, wherein the code rate and constraints is of the type 32/33(d=0, k=16), where a 2-bit partition of the pre-encoded codeword is formed and the maximum number of bits flipped simultaneously in a single codeword is three.

22. The computer hard disk drive according to claim 18, wherein the code rate and constraints is of the type 24/25(d=0, k=12)), where a 5-bit partition of the pre-encoded codeword is formed and the maximum number of bits flipped simultaneously in a single codeword is five.

23. The computer hard disk drive according to claim 18 wherein the code rate and constraints is of the type 16/17(d=0, k=8), where a 5-bit partition of the pre-encoded codeword is formed and the maximum number of bits flipped simultaneously in a single codeword is five.

24. The computer hard disk drive according to claim 18 wherein the code rate and constraints is of the type 32/33(d=0, k=16), where a 5-bit partition of the pre-encoded codeword is formed and the maximum number of bits flipped simultaneously in a single codeword is five.