Optical receiving circuit

• US 6,018,407 A
• Filed: 05/20/1997
• Issued: 01/25/2000
• Est. Priority Date: 05/20/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nagahori, Takeshi, Hatakeyama, Ichiro
• Primary Examiner(s): Mullen, Thomas
• Application Number:
  US08/859,205
• Time in Patent Office: 980 Days
• Field of Search: 359/189, 359/161, 375/317, 375/318, 455/296, 327/309, 327/323, 330/75, 330/98, 330/99
• US Class Current: 398/209
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier

Abstract

An optical receiving circuit comprising a plurality of amplifying circuits successively connected in a multiple stage form, each of the plurality of amplifying circuits having an offset compensating function. The optical receiving circuit includes offset compensating circuits respectively arranged in the plurality of amplifying circuits. Time constants of the offset compensating circuits are set in such a manner that the time constant of an offset compensating circuit arranged at one stage is smaller than that of an offset compensating circuit arranged at the previous stage.

Claims

1. An optical receiving circuit comprising a plurality of amplifying circuits each having an offset compensating function, said plurality of amplifying circuits being successively connected in a multistage form;

the time constant of an offset compensating circuit arranged in an amplifying circuit at each stage being set in such a manner that the time constant of an offset compensating circuit in an amplifying circuit at one stage is smaller than that of an offset compensating circuit in an amplifying circuit at the previous stage.

2. The optical receiving circuit of claim 1, wherein said offset compensating circuit comprises a circuit for detecting a peak level of a positive-phase output signal from an amplifying circuit at each stage and a circuit for detecting a peak level of a negative-phase output signal therefrom, and performs a feedback operation to equalize said peak levels detected;

the time constant of each of said peak detecting circuits being set in such a manner that the time constant of a peak level detecting circuit in an amplifying circuit at one stage is smaller than that of a peak level detecting circuit in an amplifying circuit at the previous stage.

3. The optical receiving circuit of claim 1, wherein said offset compensating circuit comprises a circuit for detecting an average value of a positive-phase output signal and an average value of a negative-phase output signal from an amplifying circuit at each stage, and then performs a feedback operation to equalize said average values detected;

the time constant of said average value detecting circuit being set in such a manner that the time constant of an average detecting circuit in an amplifying circuit at one stage is smaller than that of an average detecting circuit in an amplifying circuit at the previous stage.

4. The optical receiving circuit of claim 1, wherein said offset compensating circuit comprises a circuit for detecting a peak level of a positive-phase output signal from an amplifying circuit at a previous stage and a circuit for detecting a peak level of a negative-phase output signal therefrom;

said offset compensating circuit adding said detected peak level of said positive-phase output signal to a negative phase input of an amplifying circuit at a stage including said offset compensating circuit and adding said detected peak level of said negative-phase output signal to a positive-phase input of an amplifying circuit at said stage including said offset compensating circuit;

the time constant of each of said peak level detecting circuits being set in such a manner that the time constant of a peak level detecting circuit in an amplifying circuit at one stage is smaller than that of a peak level detecting circuit in an amplifying circuit at the previous stage.

5. An optical receiving circuit of claim 1, wherein said offset compensating circuit comprises a circuit for detecting a peak level of an output signal from an amplifying circuit at a previous stage and a circuit for detecting a bottom level of an output signal therefrom;

said compensating circuit differentially amplifying an intermediate value of said peak level and said bottom level detected as a reference input for an amplifying circuit at a stage including said offset compensating circuit;

the time constant of said peak level detecting circuit being set in such a manner that the time constant in an amplifying circuit at one stage is smaller than that in an amplifying circuit at the previous stage;

the time constant of said bottom level detecting circuit being set in such a manner that the time constant in an amplifying circuit at one stage is smaller than that in an amplifying circuit at the previous stage.

6. An optical receiving circuit comprising;

photo diode for converting an input optical signal into an electrical signal; and

a plurality of amplifying circuits successively connected in a multistage for converting said electrical signal converted by said photo diode into bipolar codes;

said plurality of amplifying circuits respectively including an amplifier and an offset compensating circuit;

said offset compensating circuit including;

a first peak level detecting circuit for detecting a peak level of a positive-phase output signal from said amplifier;

a second peak level detecting circuit for detecting a peak level of a negative-phase output signal from said amplifier; and

a differential amplifier for feeding a differential output signal of said peak level detected by said first peak level detecting circuit back to a positive-phase input and for feeding a differential output signal of said peak level detected by said second peak level detecting circuit back to a negative-phase input, wherein said photo diode is connected to one of the positive-phase and negative-phase inputs of the amplifier of a first one of said amplifying circuits.

7. An optical receiving circuit comprising;

a photo diode for converting an input optical signal into an electrical signal; and

a plurality of amplifying circuits successively connected in a multistage for converting said electrical signal converted by said photo diode into bipolar codes;

said plurality of amplifying circuits respectively including an amplifier and an offset compensating circuit;

said offset compensating circuit including;

a first peak level detecting circuit for detecting a peak level of a positive-phase output signal from said amplifier;

a second peak level detecting circuit for detecting a peak level of a negative-phase output signal from said amplifier; and

a differential amplifier for feeding a differential output signal of said peak level detected by said first peak level detecting circuit back to a positive-phase input and for feeding a differential output signal of said peak level detected by said second peak level detecting circuit back to a negative-phase input, wherein the time constant at each stage is set such that the time constant of an offset compensating circuit arranged at one stage is larger than the time constant of an offset compensating circuit arranged at the following stage.

8. An optical receiving circuit comprising:

a photo diode for converting an input optical signal into an electrical signal; and

a plurality of amplifying circuits successively connected in a multistage for converting said electrical signal converted by said photo diode into bipolar codes;

said plurality of amplifying circuits respectively including an amplifier and an offset compensating circuit;

said offset compensating circuit including;

an average value detecting circuit for detecting a first average value of a positive-phase output signal from said amplifier and a second average value of a negative-phase output signal from said amplifier; and

a differential amplifier for controlling said amplifier using said first and second average values.

9. The optical receiving circuit of claim 8, wherein the time constant at each stage is set such that the time constant of an offset compensating circuit arranged at one stage is larger than the time constant of an offset compensating circuit arranged at the following stage.

10. An optical receiving circuit comprising;

a photo diode for converting an input optical signal into an electrical signal; and

a plurality of amplifying circuits successively connected in a multistage for converting said electrical signal converted by said photo diode into bipolar codes;

said plurality of amplifying circuits respectively including an amplifier and an offset compensating circuit;

said offset compensating circuit including;

a first peak level detecting circuit for detecting a peak level of a positive-phase output signal of one amplifier to add said detected peak level to a negative-phase input signal of the following amplifier; and

a second peak level detecting circuit for detecting a peak level of a negative-phase output signal of said one amplifier to add said detected peak level to a positive-phase input signal of said following amplifier, wherein the time constant at each stage is set such that the time constant of an offset compensating circuit arranged at one stage is larger than the time constant of an offset compensating circuit arranged at the following stage.

11. An optical receiving circuit comprising:

a photo diode for converting an input optical signal into an electrical signal; and

a plurality of amplifying circuits successively connected in a multistage for amplifying a unipolar receive digital signal from said photo diode;

said plurality of amplifying circuits respectively including a limiter amplifier and an offset compensating circuit;

said offset compensating circuit including;

a peak level detecting circuit for detecting a peak level of an output signal to said amplifier;

a bottom level detecting circuit for detecting a bottom level of said output signal to said amplifier; and

a resistance voltage divider for dividing said output signal from said peak level detecting circuit and said output signal from said bottom level detecting circuit to supply an intermediate value as a reference to said limiter amplifier, wherein the time constant of a peak level detecting circuit arranged at one stage is larger than the time constant of a peak level detecting circuit arranged at the following stage; and

wherein the time constant of a bottom level detecting circuit arranged at said one stage is larger than the time constant of a bottom level detecting circuit arranged at said following stage.