Nonvolatile configuration cells and cell arrays

• US 6,018,476 A
• Filed: 11/18/1997
• Issued: 01/25/2000
• Est. Priority Date: 09/16/1996
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda U., Sansbury, James D.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/972,369
• Time in Patent Office: 798 Days
• Field of Search: 365/185.28, 365/185.25, 365/185.23
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store she configuration information for a programmable logic device (121).

Claims

1. A memory comprising:

a tunnel diode providing a source of electrons;

an erase node coupled to provide voltages to said tunnel diode;

a pull-down device coupled between an output node and a first conductor, wherein the pull-down device reduces an output voltage at the output node;

a programmable memory element, coupled between said output node and a second conductor; and

a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element.

2. The memory of claim 1 wherein said second conductor is at a voltage level above said first conductor during normal operation.

3. The memory of claim 1 wherein said pull-down device is a thin film transistor having a gate coupled to said gate of said programmable memory element.

4. The memory of claim 1 wherein to program said programmable memory element, a program voltage is coupled to a control gate of said programmable memory element, an assist voltage is placed on said first conductor and said second conductor, and said erase node is grounded.

5. The memory of claim 4 wherein said assist voltage is at a level of a VDD voltage or greater.

6. The memory of claim 1 wherein to erase said programmable memory element, a control gate of said programmable memory element is set at ground or less and said erase node is coupled to an erase voltage.

7. The memory of claim 1 wherein an intermediate voltage is placed on control gates of unselected neighboring memory cells.

8. The memory of claim 1 wherein said pull-down device is a thin film transistor sharing a floating gate with said programmable memory element.

9. The memory of claim 1 wherein the programmable memory element is a floating gate device.

10. The memory of claim 1 wherein the programmable memory element is an EEPROM, Flash, or EPROM device.

11. The memory of claim 1 wherein in a layout of the memory, the first and second conductors are positioned parallel to each other.

12. The memory of claim 1 wherein a logic high level at the output node is statically held by the programmable memory element.

13. A programmable logic device comprising a memory as recited in claim 1.

14. The memory of claim 1 wherein the pull-down device provides a first resistance value, between a second resistance value of the programmable memory element in an erased state and a third resistance value of the programmable memory element in a programmed state.

15. The memory of claim 1 wherein the pull-down device provides a resistance of more than about one megaohm.

16. The memory of claim 1 wherein the pull-down device provides a resistance of more than about one hundred megaohms.

17. The memory of claim 1 wherein the pull-down device provides a resistance of more than about one gigaohm.

18. The memory of claim 1 wherein the pull-down device provides a resistance of more than about twenty gigaohms.

19. The memory of claim 1 wherein the pull-down device provides a resistance of about one teraohm or more.

20. A memory comprising:

a tunnel diode providing a source of electrons;

an erase node coupled to provide voltages to said tunnel diode;

a pull-down device coupled between an output node and a first conductor;

a programmable memory element, coupled between said output node and a second conductor; and

a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element, wherein a pull-down current through the pull-down device provides a static logic low output at the output node.

21. A memory comprising:

a tunnel diode providing a source of electrons;

an erase node coupled to provide voltages to said tunnel diode;

a pull-down device coupled between an output node and a first conductor;

a programmable memory element, coupled between said output node and a second conductor; and

a tunnel dielectric coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element, wherein a pull-down current through the pull-down device reduces a voltage level at the output node.

22. A memory comprising:

a tunnel diode providing a source of electrons;

an erase node coupled to provide voltages to said tunnel diode;

a pull-down device coupled between an output node and a first conductor;

a programmable memory element, coupled between said output node and a second conductor; and

a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element, wherein the pull-down device discharges current to the first conductor.