Nonvolatile configuration cells and cell arrays
First Claim
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1. A memory comprising:
- a tunnel diode providing a source of electrons;
an erase node coupled to provide voltages to said tunnel diode;
a pull-down device coupled between an output node and a first conductor, wherein the pull-down device reduces an output voltage at the output node;
a programmable memory element, coupled between said output node and a second conductor; and
a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element.
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Abstract
A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store she configuration information for a programmable logic device (121).
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Citations
22 Claims
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1. A memory comprising:
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a tunnel diode providing a source of electrons; an erase node coupled to provide voltages to said tunnel diode; a pull-down device coupled between an output node and a first conductor, wherein the pull-down device reduces an output voltage at the output node; a programmable memory element, coupled between said output node and a second conductor; and a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory comprising:
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a tunnel diode providing a source of electrons; an erase node coupled to provide voltages to said tunnel diode; a pull-down device coupled between an output node and a first conductor; a programmable memory element, coupled between said output node and a second conductor; and a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element, wherein a pull-down current through the pull-down device provides a static logic low output at the output node.
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21. A memory comprising:
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a tunnel diode providing a source of electrons; an erase node coupled to provide voltages to said tunnel diode; a pull-down device coupled between an output node and a first conductor; a programmable memory element, coupled between said output node and a second conductor; and a tunnel dielectric coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element, wherein a pull-down current through the pull-down device reduces a voltage level at the output node.
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22. A memory comprising:
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a tunnel diode providing a source of electrons; an erase node coupled to provide voltages to said tunnel diode; a pull-down device coupled between an output node and a first conductor; a programmable memory element, coupled between said output node and a second conductor; and a tunnel dielectric, coupled between said tunnel diode and a gate of said programmable memory element, wherein said tunnel dielectric passes electrons between said tunnel diode and said gate of said programmable memory element, wherein the pull-down device discharges current to the first conductor.
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Specification