High efficiency redundancy scheme for semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a plurality of normal memory cells;
means for activating said memory cells (XDEC) in response to an externally applied address;
a plurality of redundant memory cells;
memory and comparison means (XRED) comprising first means for storing an address of a failed memory cell existing within said plurality of normal memory cells and means for comparing said externally applied address with said failed memory cell address;
redundant memory cell selection means (XRDN) for selecting any one of a plurality of said redundant memory cells in response to an output signal output from said memory and comparison means (XRED); and
redundant memory cell activating means (RXDC) for activating said redundant memory cell, responsive to an output of said memory and comparison means.
2 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor memory device is provided that includes a plurality of normal memory cells, a device for activating the memory cells in response to an externally applied address and a plurality of redundant memory cells. A memory and comparison device may include a device for storing an address of a failed memory cell existing within a plurality of normal memory cells and a device for comparing the externally applied address with the failed memory cell address. A redundant memory cell selection device may select any one of a plurality of redundant memory cells in response to an output signal output from the memory and comparison device. A redundant memory cell activating device may activate the redundant memory cell, responsive to an output of the memory and comparison device.
13 Citations
20 Claims
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1. A semiconductor memory device comprising:
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a plurality of normal memory cells; means for activating said memory cells (XDEC) in response to an externally applied address; a plurality of redundant memory cells; memory and comparison means (XRED) comprising first means for storing an address of a failed memory cell existing within said plurality of normal memory cells and means for comparing said externally applied address with said failed memory cell address; redundant memory cell selection means (XRDN) for selecting any one of a plurality of said redundant memory cells in response to an output signal output from said memory and comparison means (XRED); and redundant memory cell activating means (RXDC) for activating said redundant memory cell, responsive to an output of said memory and comparison means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor memory device comprising:
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a plurality of normal memory cells; an activation device that activates said memory cells (XDEC) in response to an externally applied address; a plurality of redundant memory cells; a memory and comparison device (XRED) comprising a storage device that stores an address of a failed memory cell existing within said plurality of normal memory cells and a comparison device that compares said externally applied address with said failed memory cell address; a redundant memory cell selection device (XRDN) that selects any one of said plurality of redundant memory cells in response to an output signal output from said memory and comparison device (XRED); and a redundant memory cell activating device (RXDC) that activates said redundant memory cell, responsive to an output of said memory and comparison device.
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Specification