Automatic gain control circuit and method for full gain restart

• US 6,018,554 A
• Filed: 04/24/1997
• Issued: 01/25/2000
• Est. Priority Date: 05/17/1996
• Status: Expired due to Term

• Current Assignee: Swayze W. Daniel Jr
• Original Assignee: Texas Instruments, Inc.
• Inventors: Glover, Kerry C.
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US08/840,649
• Time in Patent Office: 1,006 Days
• Field of Search: 375/345, 455/234.1, 360/46, 360/67
• US Class Current: 375/345
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence

Abstract

An automatic gain control circuit (44) is provided for generating an output gain signal (64) in a control loop. The control loop may a continuous-time control loop or a sampled-time control loop. The automatic gain control circuit (144) includes a gain control circuit (100), an amplifier circuit such as a first amplifier (120) or a second amplifier (122), a control circuit (126), and a low pass filter (84). The gain control circuit (144) receives a read signal and generates an error signal in response. The first amplifier (120) receives the error signal and generates an amplified error signal. The control circuit (126) controls various switches, such as a first switch (100) and a second switch (102), so that the amplified error signal and the error signal may be provided to the low pass filter (84) during different periods. The amplified error signal is provided during a first period that is shorter than the response time of the control loop. The error signal is provided next after the first period and after a second period that is longer than the response time of the control loop. The low pass filter (84) filters these signals and generates the output gain signal (64).

Claims

1. An automatic gain control circuit for use in a control loop, the automatic gain control circuit comprising:

a gain control circuit operable to receive a read signal and to generate an error signal in response;

an amplifier circuit operable to receive the error signal and to generate an amplified error signal in response;

a control circuit operable to provide the amplified error signal during a first period that is shorter than the response time of the control loop, the control circuit operable to provide the error signal after a second period, the second period occurring after the first period, the second period being longer than the response time of the control loop; and

a filter circuit operable to receive the signal provided by the control circuit and to generate an output gain signal.

2. The automatic gain control circuit of claim 1, wherein the read signal is a continuous-time read signal.

3. The automatic gain control circuit of claim 2, wherein the continuous-time read signal is provided by a low pass filter.

4. The automatic gain control circuit of claim 1, wherein the read signal is a sampled read signal.

5. The automatic gain control circuit of claim 4, wherein the sampled read signal is provided by a detector.

6. The automatic gain control circuit of claim 4, wherein the sampled read signal is provided as the output of an error circuit.

7. The automatic gain control circuit of claim 1, wherein the filter is a low pass filter.

8. The automatic gain control circuit of claim 1, wherein the first amplifier is provided with a programmable full gain signal.

9. The automatic gain control circuit of claim 1, wherein the first period and the second period are programmable periods.

10. The automatic gain control circuit of claim 1, wherein the gain control circuit comprises:

a rectifier circuit operable to rectify the read signal and to generate a rectified read signal;

a comparator operable to receive the rectified read signal and a threshold signal and to provide a comparison signal in response;

an adder circuit operable to receive the rectified read signal and the threshold signal and to subtract the threshold signal from the rectified read signal to generate an offset signal; and

a multiplier circuit operable to multiply the offset signal and a gain signal to generate an error signal.

11. An automatic gain control circuit for use in controlling a first control loop and a second control loop, the automatic gain control circuit comprising:

a first gain control circuit operable to receive a continuous-time read signal and to generate a continuous-time error signal in response;

a second gain control circuit operable to receive a sampled read signal and to generate a sampled error signal in response;

a first amplifier circuit operable to receive the continuous-time error signal and to generate an amplified continuous-time error signal in response;

a second amplifier circuit operable to receive the sampled error signal and to generate an amplified sampled error signal in response;

a control circuit operable to provide the amplified continuous-time error signal during a first period that is shorter than the response time of the first control loop, the control circuit operable to provide the continuous-time error signal after a second period, the second period occurring after the first period, the second period being longer than the response time of the first control loop, the control circuit operable to provide the amplified sampled error signal during a third period that is shorter than the response time of the second control loop, the control circuit operable to provide the sampled error signal after a fourth period, the fourth period occurring after the third period, the fourth period being longer than the response time of the second control loop; and

a filter circuit operable to receive the signal provided by the control circuit and to generate an output gain signal.

12. The automatic gain control circuit of claim 11, wherein the continuous-time read signal is provided by a low pass filter.

13. The automatic gain control circuit of claim 11, wherein the sampled read signal is provided by a detector.

14. The automatic gain control circuit of claim 11, wherein the sampled read signal is provided as the output of an error circuit.

15. The automatic gain control circuit of claim 11, wherein the filter is a low pass filter.

16. The automatic gain control circuit of claim 11, wherein the first amplifier is operable to receive a programmable, first full gain signal and the second amplifier is operable to receive a programmable, second full gain signal.

17. The automatic gain control circuit of claim 11, wherein the first period, the second period, the third period, and the fourth period are programmable periods.

18. A method for full gain restart using an automatic gain control circuit in a control loop, the method comprising the steps of:

receiving a read signal;

rectifying the read signal to generate a rectified read signal;

comparing the rectified read signal to a threshold value;

generating an offset signal by subtracting the threshold value from the rectified read signal;

generating an error signal by multiplying the offset signal by a gain signal, the gain signal provided in response to the comparing the rectified read signal step;

amplifying the error signal to generate an amplified error signal;

providing the amplified error signal to a filter during a first period that is shorter than the response time of the control loop; and

providing the error signal to the filter after a second period, the second period occurring after the first period, the second period being longer than the response time of the control loop.

19. The method of claim 18 wherein, the read signal is a continuous-time read signal.

20. The method of claim 18 wherein, the read signal is a sampled read signal.