Method to back annotate programmable logic device design files based on timing information of a target technology
First Claim
1. A method of verifying an operation of a mask programmed integrated circuit (MPIC) implementation of a programmable logic device (PLD) implementation of a circuit design using a computer system, said method comprising:
- generating a PLD simulation model of said circuit design as implemented in a PLD;
back annotating said PLD simulation model using timing information corresponding to said MPIC implementation to generate an MPIC simulation model; and
verifying said operation by simulating said MPIC simulation model.
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Abstract
One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.
38 Citations
7 Claims
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1. A method of verifying an operation of a mask programmed integrated circuit (MPIC) implementation of a programmable logic device (PLD) implementation of a circuit design using a computer system, said method comprising:
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generating a PLD simulation model of said circuit design as implemented in a PLD; back annotating said PLD simulation model using timing information corresponding to said MPIC implementation to generate an MPIC simulation model; and verifying said operation by simulating said MPIC simulation model. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification