Apparatus for filtering a signal utilizing recursion and decimation

• US 6,018,754 A
• Filed: 11/23/1998
• Issued: 01/25/2000
• Est. Priority Date: 04/10/1996
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Yung-Lung, Jen, Chein-Wei, Tai, Chiao-Yen, Lee, Hwan-Rei
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/197,688
• Time in Patent Office: 428 Days
• Field of Search: 708/303, 708/313, 708/316, 708/321
• US Class Current: 708/316
• CPC Class Codes: H03H 17/0266 Filter banks

Abstract

Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Claims

1. A digital signal filter bank device for filtering an external input signal to generate a filtered digital output signal, the device comprising:

an input signal selector to select between the external input signal and a low-pass filtered feedback signal to provide a filter input signal;

a filter bank to receive the filter input signal and to filter the filter input signal to concurrently generate both a high-pass filtered signal and a low-pass filtered signal, wherein the low-pass filtered signal includes a low-pass filtered output signal and the low-pass filtered feedback signal; and

a frequency band selector to receive both the high-pass filtered signal and the low-pass filtered output signal directly from the filter bank to generate the filtered digital output signal;

wherein the filter bank includes a logic circuit to apply a distributed arithmetic algorithm to the filter input signal to generate first and second summations of product terms respectively representing the high-pass filtered signal and the low-pass filtered signal; and

wherein the filter bank further includes a low-pass filter to generate the low-pass filtered feedback signal using a decimated sampling rate.

2. The digital signal filter bank device of claim 1, wherein the filter bank includes a plurality of filters organized as one bank of filters, wherein the plurality of filters generate a plurality of filtered outputs having a plurality of frequency bands, and wherein each of the plurality of frequency bands, at most, slightly overlaps another of the plurality of frequency bands.

3. The digital signal filter bank device of claim 2, wherein the plurality of filters includes a high-pass filter to generate the high-pass filtered signal and a low-pass filter to generate the low-pass filtered signal.

4. The digital signal filter bank device of claim 3, wherein the high-pass filter and the low-pass filter simultaneously receive the filter input signal.

5. The digital signal filter bank device of claim 2, wherein the plurality of filters includes a high-pass filter to generate the high-pass filtered signal, a low-pass filter to generate the low-pass filtered signal, and a plurality of band-pass filters to generate a plurality of band-pass filtered signals, and wherein the frequency band selector is further responsive to the plurality of band-pass filtered signals to generate the filtered digital output signal.

6. The digital signal filter bank device of claim 5, wherein the high-pass filter, the low-pass filter, and the plurality of band-pass filters simultaneously receive the filter input signal.

7. The digital signal filter bank device of claim 5,

wherein the frequency band selector includes a first plurality of arrays of tri-state buffers having a plurality of output lines, wherein the first plurality of arrays of tri-state buffers includes:

a first array of tri-state buffers,

a second array of tri-state buffers, and

a second plurality of arrays of tri-state buffers,

wherein the plurality of output lines are tied to form a device output to carry the device output signal,

wherein the first array of tri-state buffers includes a first input to receive the high-pass filtered signal,

wherein the second array of tri-state buffers includes a second input to receive the low-pass filtered signal,

wherein the second plurality of arrays of tri-state buffers each includes a third input to receive a corresponding one of the plurality of band-pass filtered signals, and

wherein the first plurality of arrays of tri-state buffers include a plurality of respective output enable inputs to independently control respective selection of the high-pass filtered signal, low-pass filtered signal, and plurality of band-pass filtered signals for transmission on the device output.

8. The digital filter bank device of claim 7, wherein the low-pass filtered output signal is one of a sequence of low-pass filtered feedback signals, and the low-pass filtered signal received by the second array of tri-state buffers is a final low-pass filtered feedback signal in the sequence of low-pass filtered feedback signals.

9. The digital filter bank device of claim 2, wherein each of the filters includes first and second signal selectors, a pole signal processor, a parallel-to-serial converter, a shift register, first and second memories, and a zero signal processor, wherein:

the first signal selector includes a first input to receive the filter input signal, a second input to receive a first memory data output from the first memory, and an output to selectively provide the first memory data output as a first selected signal,

the pole signal processor includes a first input to receive the first selected signal and a second input to receive a second selected output from the second signal selector, wherein said pole signal processor generates a pole signal for inclusion in the summations of product terms according to the distributed arithmetic algorithm,

the second signal selector has a first input to receive the pole signal, a second input to receive the first memory data output, and an output to transmit the selected first memory data output as a second selected signal,

the parallel-to-serial converter has an input to receive the pole signal, wherein said parallel-to-serial converter converts the pole signal from a parallel format to a serial format including a plurality of bits of data,

the shift register has an input to receive the serial format pole signal, and includes an address synthesizer to form first and second memory addresses using bits of data of the serial format pole signal,

the first memory includes first addressing logic to retrieve first digital filter characteristic coefficient data stored in the shift register means and to store the retrieved first digital filter characteristic coefficient data as first memory data,

the second memory includes second addressing logic to retrieve second digital filter characteristic coefficient data stored in the shift register means and to store the retrieved second digital filter characteristic coefficient data as second memory data, and

the zero signal processor includes an input to receive the second memory data, processing logic to process the second memory data as summations of product terms according to the distributed arithmetic algorithm, and an output port to provide the processed second memory data as the high-pass filtered signal and the low-pass filtered signal.

10. The digital filter bank device of claim 9, wherein the zero signal processor output port provides the processed second memory data as the high-pass filtered signal, the low-pass filtered signal, and a band-pass filtered signal.

11. The digital filter bank device of claim 10, wherein the first signal selector includes first and second arrays of tri-state buffers having respective first and second output lines, wherein the first and second output lines are tied to form a first select output, and wherein the first and second arrays of tri-state buffers include respective first and second output enable inputs to independently control provision of the first selected signal to the first select output.

12. The digital filter bank device of claim 10, wherein the second signal selector includes first and second arrays of tri-state buffers having respective first and second output lines, wherein the first and second output lines are tied to form a second select output, and wherein the first and second arrays of tri-state buffers include respective first and second output enable inputs to independently control provision of the second selected signal to the second select output.

13. The digital filter bank device of claim 10, wherein the pole signal processor comprises an array of registers, an array of adders, a set of stage register arrays, and an array of AND-OR logic gates, wherein:

the set of stage register arrays includes an input circuit to receive the second selected signal and to latch the second selected signal for provision to the array of AND-OR logic gates,

the array of AND-OR logic gates includes an input port to receive the latched second selected signal, a signal conditioner to condition the latched second selected signal, and an output port to provide the conditioned second selected signal to the array of adders,

the array of adders includes a first input port to receive the conditioned second selected signal, a second input port to receive the first selected signal, and addition logic to add the conditioned second selected signal and the first selected signal to generate a selected signal sum for provision to the array of registers, and

the array of registers includes an input circuit to receive the selected signal sum and to latch the selected signal sum as the pole signal, according to a clock signal.

14. The digital filter bank device of claim 10, wherein the first memory is a read-only memory.

15. The digital filter bank device of claim 10, wherein the second memory is a read-only memory.

16. The digital filter bank device of claim 10, wherein the first memory is a programmable array logic memory device.

17. The digital filter bank device of claim 10, wherein the second memory is a programmable array logic memory device.

18. The digital filter bank device of claim 9, wherein the zero signal processor includes an array of registers, an array of adders, a set of stage register arrays, and an array of AND-OR logic gates, wherein:

the array of AND-OR logic gates includes an input port to receive a register output from the set of stage register arrays, a signal conditioner to condition the register output to produce a conditional pole signal, an output port to provide the conditioned pole signal to the array of adders,

the array of adders includes an input port to receive the conditioned pole signal and the second memory data, addition logic to add the conditioned pole signal and the second memory data to produce a summation, and an output port to provide the summation to the array of registers,

the array of registers includes an input circuit to receive and latch the summation, and synchronous logic to provide the summation to the set of stage register arrays according to a clock signal, and

the set of stage register arrays includes an input port to receive the latched summation, and output circuitry to provide the latched summation to the frequency bank selector as the high-pass filtered signal and the low-pass filtered signal.

19. The digital filter bank device of claim 18, wherein the zero signalling processor further includes output circuitry to provide the latched summation to the frequency bank selector as a band-pass filtered signal.

20. The digital signal filter bank device of claim 1, wherein the filter bank includes a plurality of filter organized as a plurality of banks of filters, wherein the plurality of filters generate a plurality of filtered outputs having a plurality of frequency bands, and wherein each of the plurality of frequency bands, at most, slightly overlaps another of the plurality of frequency bands.

21. The digital signal filter bank device of claim 1, further comprising an analog-to-digital converter to convert the external input signal to a digital format for processing by the input signal selector.

22. The digital signal filter bank device of claim 1,

wherein the input signal selector includes first and second arrays of tri-state buffers having respective first and second output lines,

wherein the first and second output lines are tied to form a selector output line to carry the filter input signal,

wherein the first array of tri-state buffers includes a first input to receive the external input signal,

wherein the second array of tri-state buffers includes a second input to receive the low-pass filtered feedback signal, and

wherein the first and second arrays of tri-state buffers include an output enable input to control selection between the external input signal and the low-pass filtered feedback signal, to provide the filter input signal.

23. The digital signal filter bank device of claim 1,

wherein the low-pass filtered feedback signal is a plurality of feedback signals,

wherein the input signal selector includes a first plurality of arrays of tri-state buffers having a first plurality of output lines, wherein the first plurality of arrays includes

a first array of tri-state buffers having a corresponding first output line, and

a second plurality of arrays of tri-state buffers having a respective second plurality of output lines;

wherein the first plurality of output lines are tied to form a selector output to carry the filter input signal,

wherein the first array of tri-state buffers includes a first input to receive the external input signal,

wherein the second plurality of arrays each includes a second input to receive a corresponding one of the plurality of feedback signals, and

wherein the first plurality of arrays of tri-state buffers includes an output enable input to control selection between the external input signal and the plurality of feedback signals, to provide the filter input signal.

24. The digital signal filter bank device of claim 1,

wherein the frequency band selector includes first and second arrays of tri-state buffers having respective first and second output lines,

wherein the first and second output lines are tied to form a device output to carry the device output signal,

wherein the first array of tri-state buffers includes a first input to receive the high-pass filtered signal,

wherein the second array of tri-state buffers includes a second input to receive the low-pass filtered signal, and

wherein the first and second arrays of tri-state buffers include respective first and second output enable inputs to independently control respective selection of the high-pass filtered signal and the low-pass filtered signal for transmission on the device output.

25. The digital filter bank device of claim 24, wherein the low-pass filtered output signals is one of a sequence of low-pass filtered feedback signals and the low-pass filtered signal received by the second array of tri-state buffers is a final low-pass filtered feedback signal in the sequence of low-pass filtered feedback signals.