Flexible buffering scheme for inter-module on-chip communications

• US 6,018,782 A
• Filed: 07/14/1997
• Issued: 01/25/2000
• Est. Priority Date: 07/14/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hartmann, Alfred C.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US08/892,415
• Time in Patent Office: 925 Days
• Field of Search: 395/200.81, 395/800.43, 395/311, 370/258, 370/403-406, 709/251, 712/43, 710/131, 710/160, 710/129
• US Class Current: 710/310
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A single chip integrated circuit comprises a plurality of modules interconnected in an on-chip network. The modules are processors or memory devices or hybrids. An inter-module link provides an electrical path for data communication among the modules. The modules are connected to the inter-module link by inter-module ports, with at least one inter-module port coupled between an associated module and the inter-module link. The inter-module link electrically couples the inter-module ports and provides a communications pathway between the modules. Each inter-module port provides a common, universal interface to any of the modules, i.e., modules of different types are connectable to any inter-module port. Each inter-module port operates to receive data from the inter-module link, to determine if the data from the inter-module link is addressed to the associated module, to provide the data from the inter-module link to the associated module if the inter-module port determines that the data from the inter-module link is addressed to the associated module, to accept data from the associated module for transmission on the inter-module link, and to transmit the data from the associated module on the inter-module link. The on-chip network may also include an inter-module network switch for joining circuits of the inter-module link and routing data packets from one inter-module links to another or an inter-chip network bridge to join two single chip integrated circuits into a single communications network and route data packets from modules on one computer chip to modules on another computer chip.

Claims

1. A system for interconnecting a plurality of modules on a single computer chip in an on-chip network comprising:

a inter-module link providing an electrical path for data communication;

a plurality of modules comprised on said chip, wherein each of said plurality of modules is different;

a plurality of inter-module ports, wherein at least one inter-module port is coupled between an associated module and said inter-module link;

wherein said inter-module link electrically couples said inter-module ports, wherein said inter-module link is configured to provide a communications pathway between said modules;

wherein each of said plurality of inter-module ports provide a common interface to each of said associated modules and to said inter-module link;

wherein said each of said plurality of inter-module ports is configured to be connectable to any of said plurality of modules on a side of said inter-module port opposite a side coupled to said inter-module link.

2. The system of claim 1,

wherein each of said inter-module ports is operable to (i) receive data from said inter-module link, (ii) determine if said data from said inter-module link is addressed to said associated module, (iii) provide said data from said inter-module link to said associated module if said inter-module port determines that said data from said inter-module link is addressed to said associated module, (iv) accept data from said associated module for transmission on said inter-module link, and (v) transmit said data from said associated module on said inter-module link.

3. The system of claim 2, wherein each inter-module port includes:

an off-ramp demultiplexer for coupling to said inter-module link, wherein said off-ramp demultiplexer receives said data from said inter-module link;

an on-ramp multiplexer for coupling to said inter-module link and for providing data to said inter-module link, wherein said on-ramp multiplexer is further coupled to said off-ramp demultiplexer, wherein said off-ramp demultiplexer is operable to provide data to said on-ramp multiplexer;

an input buffer coupled to said off-ramp demultiplexer, wherein said input buffer includes connections for coupling to said module;

an output buffer coupled to said on-ramp multiplexer, wherein said output buffer includes connections for coupling to said module; and

wherein said off-ramp demultiplexer is operable to receive said data from said inter-module link and demultiplex a portion of said data from said inter-module link which comprises data intended for said module and provide said data intended for said module to said input buffer;

wherein said input buffer is operable to receive and store said data intended for said module and provide said data intended for said module to said module;

wherein said input buffer is operable to receive and store data from said module and provide said data from said module to said on-ramp multiplexer;

wherein said on-ramp multiplexer is operable to receive said data from said module and multiplex said data from said module with other data received from said off-ramp demultiplexer to form multiplexed data, wherein said on-ramp multiplexer is operable to provide said multiplexed data to said inter-module link.

4. The system of claim 2, further comprising:

an inter-module network switch for coupling a plurality of inter-module links.

5. The system of claim 4, wherein said inter-module network switch includes,

a plurality of connectors for connecting to said plurality of inter-module links;

an input buffer and an output buffer for coupling to each of said plurality of inter-module links;

switching logic coupled to each of said input buffers and coupled to each of said output buffers, wherein said switching logic is configured to transfer communications from a first input buffer coupled to a first inter-module link to a second output buffer coupled to a second inter-module link; and

a controller coupled to said switching logic for controlling operations of said switching logic.

6. The system of claim 5,

wherein said plurality of connectors includes a first subset of connectors designed to only receive data, wherein said plurality of connectors includes a second subset of connectors designed to only transmit data;

wherein said first subset of connectors couple to a first plurality of inter-module links which provide data to said first subset of connectors;

wherein said second subset of connectors couple to a second plurality of inter-module links which provide data to said second subset of connectors.

7. The system of claim 6,

wherein said controller is operable to control transfer data from said first input buffer coupled to said first inter-module link to said second output buffer coupled to said second inter-module link.

8. The system of claim 7,

wherein said communications include a data packet with an associated address which uniquely identifies a for said data packet, and

wherein said controller is operable to read said associated address, determine said destination for said data packet, and direct said switching logic to route said data packet to said destination.

9. The system of claim 4, further comprising:

an inter-chip network bridge for coupling two computer chips.

10. The system of claim 9, wherein said inter-chip network bridge includes:

a plurality of connectors for coupling to a plurality of corresponding connectors comprised on said second computer chip;

one or more output buffers operable to accept outgoing data destined for an address on said second computer chip;

one or more input buffers operable to receive incoming data destined for an associated address on said associated computer chip;

a switching logic coupled to each of said output buffers, wherein said switching logic is further coupled to each of said input buffers, wherein said switching logic is operable to transfer said outgoing data from a first output buffer to said second computer chip, wherein said switching logic is further operable to receive said incoming data from said second computer chip into a first input buffer; and

a controller coupled to control said switching logic.

11. The system of claim 10,

wherein said plurality of connectors includes a first subset of connectors designed to only receive said incoming data, wherein said plurality of connectors includes a second subset of connectors designed to only transfer said outgoing data;

wherein said first subset of connectors are operable to couple to a first plurality of connectors comprised on said second computer chip which are configured to provide said incoming data to said first subset of connectors;

wherein said second subset of connectors are operable to couple to a second plurality of connectors comprised on said second computer chip which are configured to receive said incoming data from said first subset of connectors.

12. The system of claim 1,

wherein each of said plurality of modules is selected from a group including a processor, a memory, an I/O controller, an inter-chip network bridge, a task-specific hybrid, and a task-general hybrid.

13. The system of claim 1, wherein said inter-module link is operable to transmit data on only one direction.

14. An on-chip inter-module port for coupling a module comprised on a computer chip to an inter-module link comprised on said computer chip for communications between a plurality of modules comprised on said computer chip, said inter-module port comprising:

an off-ramp demultiplexer for coupling to said inter-module link, wherein said off-ramp demultiplexer receives data from said inter-module link;

an on-ramp multiplexer for coupling to said inter-module link and for providing data onto said inter-module link, wherein said on-ramp multiplexer is further coupled to said off-ramp demultiplexer, wherein said off-ramp demultiplexer is operable to provide data to said on-ramp multiplexer;

an input buffer coupled to said off-ramp demultiplexer, wherein said input buffer includes connections for coupling to said module;

an output buffer coupled to said on-ramp multiplexer, wherein said output buffer includes connections for coupling to said module; and

wherein said off-ramp demultiplexer is operable to receive data from said inter-module link and demultiplex a portion of said data intended for said module and provide said portion of said data intended for said module to said input buffer;

wherein said input buffer is operable to receive and store said portion of said data intended for said module and provide said portion of said data intended for said module to said module;

wherein said input buffer is operable to receive and store data from said module and provide said data from said module to said on-ramp multiplexer;

wherein said on-ramp multiplexer is operable to receive said data from said module and multiplex said data from said module with other data received from said off-ramp demultiplexer to form multiplexed data, wherein said on-ramp multiplexer is operable to provide said multiplexed data to said inter-module link;

wherein said inter-module port provides a common interface to each of said plurality of modules;

wherein a module of different types is connectable to said inter-module port on a side of said inter-module port opposite a side coupled to said inter-module link.

15. The on-chip inter-module port of claim 14, further comprising:

a port controller coupled to control said operations of said off-ramp demultiplexer, said on-ramp multiplexer, said input buffer, and said output buffer.

16. The on-chip inter-module port of claim 15, wherein said port controller provides clocking signals to each of said off-ramp demultiplexer, said on-ramp multiplexer, said input buffer, and said output buffer.

17. The on-chip inter-module port of claim 15, wherein data received from said inter-module link includes addresses, wherein said module has a unique address;

wherein said port controller is operable to receive addresses of received data from said off-ramp demultiplexer and determine if said unique address of said module is present;

wherein said port controller is operable to direct said off-ramp demultiplexer to provide data associated with said unique address of said module to said input buffer if said port controller determines that said unique address of said module is present.

18. The on-chip inter-module port of claim 15, wherein data received from said inter-module link includes addresses, wherein said module has a unique address;

wherein said off-ramp demultiplexer is operable to receive addresses of received data from said inter-module link and determine if said unique address of said module is present;

wherein said off-ramp demultiplexer is operable to provide data associated with said unique address of said module to said input buffer if said off-ramp demultiplexer determines that said unique address of said module is present.

19. A system for interconnecting a plurality of modules on a single computer chip in an on-chip network comprising:

an inter-module link comprised on said chip providing an electrical path for data communication;

a plurality of modules comprised on said chip, wherein each of said modules perform operations and/or store data, wherein at least one of said plurality of modules is a processor, and wherein at least one of said plurality of modules is a memory;

a plurality of inter-module ports comprised on said chip, wherein at least one inter-module port is coupled between an associated module and said inter-module link;

wherein said inter-module link electrically couples said inter-module ports, wherein said inter-module link is configured to provide a communications pathway between said modules;

wherein each of said plurality of inter-module ports provides a common interface to each of said associated modules;

wherein modules of different types are connectable to any of said inter-module ports on a side of said inter-module port opposite a side coupled to said inter-module link.

20. The system of claim 19, wherein said inter-module link is configured to transport a plurality of data items concurrently.

21. The system of claim 19,

wherein each of said inter-module ports is operable to (i) receive data from said inter-module link, (ii) determine if said data from said inter-module link is addressed to said associated module, (iii) provide said data from said inter-module link to said associated module if said inter-module port determines that said data from said inter-module link is addressed to said associated module, (iv) accept data from said associated module for transmission on said inter-module link, and (v) transmit said data from said associated module on said inter-module link.

22. The system of claim 21, wherein each inter-module port includes:

an off-ramp demultiplexer on said chip for coupling to said inter-module link, wherein said off-ramp demultiplexer receives said data from said inter-module link;

an on-ramp multiplexer on said chip for coupling to said inter-module link and for providing data to said inter-module link, wherein said on-ramp multiplexer is further coupled to said off-ramp demultiplexer, wherein said off-ramp demultiplexer is operable to provide data to said on-ramp multiplexer;

an input buffer on said chip coupled to said off-ramp demultiplexer, wherein said input buffer includes connections for coupling to said module;

an output buffer on said chip coupled to said on-ramp multiplexer, wherein said output buffer includes connections for coupling to said module; and

wherein said off-ramp demultiplexer is operable to receive said data from said inter-module link and demultiplex a portion of said data from said inter-module link which comprises data intended for said module and provide said data intended for said module to said input buffer;

wherein said input buffer is operable to receive and store said data intended for said module and provide said data intended for said module to said module;

wherein said input buffer is operable to receive and store data from said module and provide said data from said module to said on-ramp multiplexer;

wherein said on-ramp multiplexer is operable to receive said data from said module and multiplex said data from said module with other data received from said off-ramp demultiplexer to form multiplexed data, wherein said on-ramp multiplexer is operable to provide said multiplexed data to said inter-module link.

23. The system of claim 19, further comprising:

an inter-module network switch on said chip for coupling a plurality of inter-module links.

24. The system of claim 23, wherein said inter-module network switch includes:

a plurality of connectors on said chip for connecting to said plurality of inter-module links on said chip;

an input buffer on said chip and an output buffer on said chip for coupling to each of said plurality of inter-module links;

switching logic on said chip coupled to each of said input buffers and coupled to each of said output buffers, wherein said switching logic is configured to transfer communications from a first input buffer coupled to a first inter-module link to a second output buffer coupled to a second inter-module link; and

a controller on said chip coupled to said switching logic for controlling operations of said switching logic.

25. The system of claim 24,

wherein said plurality of connectors includes a first subset of connectors designed to only receive data, wherein said plurality of connectors includes a second subset of connectors designed to only transmit data;

wherein said first subset of connectors couple to a first plurality of inter-module links which provide data to said first subset of connectors;

wherein said second subset of connectors couple to a second plurality of inter-module links which provide data to said second subset of connectors.

26. The system of claim 25,

wherein said controller is operable to control transfer data from said first input buffer coupled to said first inter-module link to said second output buffer coupled to said second inter-module link.

27. The system of claim 26,

wherein said communications include a data packet with an associated address which uniquely identifies a for said data packet, and

wherein said controller is operable to read said associated address, determine said destination for said data packet, and direct said switching logic to route said data packet to said destination.

28. The system of claim 19, further comprising:

an inter-chip network bridge on said chip for coupling said chip to a second computer chip.

29. The system of claim 28, wherein said inter-chip network bridge includes:

a plurality of connectors on said chip for coupling to a plurality of corresponding connectors comprised on said second computer chip;

one or more output buffers on said chip operable to accept outgoing data destined for an address on said second computer chip;

one or more input buffers on said chip operable to receive incoming data destined for an associated address on said chip;

a switching logic on said chip coupled to each of said output buffers, wherein said switching logic is further coupled to each of said input buffers, wherein said switching logic is operable to transfer said outgoing data from a first output buffer to said second computer chip, wherein said switching logic is further operable to receive said incoming data from said second computer chip into a first input buffer; and

a controller on said chip coupled to control said switching logic.

30. The system of claim 29,

wherein said plurality of connectors includes a first subset of connectors designed to only receive said incoming data, wherein said plurality of connectors includes a second subset of connectors designed to only transfer said outgoing data;

wherein said first subset of connectors are operable to couple to a first plurality of connectors comprised on said second computer chip which are configured to provide said incoming data to said first subset of connectors;

wherein said second subset of connectors are operable to couple to a second plurality of connectors comprised on said second computer chip which are configured to receive said incoming data from said first subset of connectors.

31. The system of claim 29,

wherein each of said plurality of modules that is not said processor or said memory is selected from a group including another processor, another memory, an I/O controller, an inter-chip network bridge, a task-specific hybrid, and a task-general hybrid.

32. A system for interconnecting a plurality of modules on a single computer chip in an on-chip network comprising:

an inter-module link comprised on said chip for providing an electrical path for data communication;

an inter-module network switch comprised on said chip for coupling a plurality of inter-module links, wherein said inter-module network switch includes;

a plurality of connectors for connecting to said plurality of inter-module links;

an input buffer and an output buffer for coupling to each of said plurality of inter-module links;

switching logic coupled to each of said input buffers and coupled to each of said output buffers, wherein said switching logic is configured to transfer communications from a first input buffer coupled to a first inter-module link to a second output buffer coupled to a second inter-module link; and

a controller coupled to said switching logic for controlling operations of said switching logic;

an inter-chip network bridge comprised on said chip for coupling two computer chips, wherein said inter-chip network bridge includes;

a plurality of connectors for coupling to a plurality of corresponding connectors comprised on said second computer chip;

one or more output buffers operable to accept outgoing data destined for an address on said second computer chip;

one or more input buffers operable to receive incoming data destined for an associated address on said associated computer chip;

a switching logic coupled to each of said output buffets, wherein said switching logic is further coupled to each of said input buffers, wherein said switching logic is operable to transfer said outgoing data from a first output buffer to said second computer chip, wherein said switching logic is further operable to receive said incoming data from said second computer chip into a first input buffer; and

a controller coupled to control said switching logic;

a plurality of modules comprised on said chip, wherein at least one of said plurality of modules is a processor, and wherein at least one of said plurality of modules is a memory;

a plurality of inter-module ports comprised on said chip, wherein at least one inter-module port is coupled between an associated module and said inter-module link;

wherein each of said inter-module ports is operable to (i) receive data from said inter-module link, (ii) determine if said data from said inter-module link is addressed to said associated module, (iii) provide said data from said inter-module link to said associated module if said inter-module port determines that said data from said inter-module link is addressed to said associated module, (iv) accept data from said associated module for transmission on said inter-module link, and (v) transmit said data from said associated module on said inter-module link;

wherein each inter-module port includes;

an off-ramp demultiplexer for coupling to said inter-module link, wherein said off-ramp demultiplexer receives said data from said inter-module link;

an on-ramp multiplexer for coupling to said inter-module link and for providing data to said inter-module link, wherein said on-ramp multiplexer is further coupled to said off-ramp demultiplexer, wherein said off-ramp demultiplexer is operable to provide data to said on-ramp multiplexer;

an input buffer coupled to said off-ramp demultiplexer, wherein said input buffer includes connections for coupling to said module;

an output buffer coupled to said on-ramp multiplexer, wherein said output buffer includes connections for coupling to said module; and

a port controller coupled to control said operations of said off-ramp demultiplexer, said on-ramp multiplexer, said input buffer, and said output buffer;

wherein said off-ramp demultiplexer is operable to receive said data from said inter-module link and demultiplex a portion of said data from said inter-module link which comprises data intended for said module and provide said data intended for said module to said input buffer;

wherein said input buffer is operable to receive and store said data intended for said module and provide said data intended for said module to said module;

wherein said input buffer is operable to receive and store data from said module and provide said data from said module to said on-ramp multiplexer;

wherein said on-ramp multiplexer is operable to receive said data from said module and multiplex said data from said module with other data received from said off-ramp demultiplexer to form multiplexed data, wherein said on-ramp multiplexer is operable to provide said multiplexed data to said inter-module link;

wherein said inter-module link electrically couples said inter-module ports, wherein said inter-module link is configured to provide a communications pathway between said modules;

wherein each of said plurality of inter-module ports provide a common interface to each of said associated modules;

wherein modules of different types are connectable to only of said inter-module ports on a side of said inter-module port opposite a side coupled to said inter-module link.

33. The system of claim 32, wherein at least one module of said plurality of modules is coupled to at least two of said plurality of inter-module ports.

34. The system of claim 33, wherein each of said at least two of said plurality of inter-module ports is coupled to a different one of said plurality of inter-module links.

35. A system for interconnecting a plurality of modules on a single computer chip in an on-chip network comprising:

an inter-module link comprised on said chip providing an electrical path for data communication;

a plurality of modules comprised on said chip, wherein each of said modules perform operations and/or store data, wherein at least one of said plurality of modules is a processor, and wherein at least one of said plurality of modules is a memory;

a plurality of inter-module ports comprised on said chip, wherein at least one inter-module port is coupled between an associated module and said inter-module link;

wherein said inter-module link electrically couples said inter-module ports, wherein said inter-module link is configured to provide a communications pathway between said modules;

wherein each of said plurality of inter-module ports provides a common interface to each of said associated modules;

wherein modules of different types are connectable to any of said inter-module ports; and

wherein at least one module of said plurality of modules is coupled to at least two of said plurality of inter-module ports on a side of said inter-module port opposite a side coupled to said inter-module link.