Semiconductor devices with CSP packages and method for making them

• US 6,020,217 A
• Filed: 02/20/1998
• Issued: 02/01/2000
• Est. Priority Date: 02/21/1997
• Status: Expired due to Fees

• Current Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Original Assignee: Daimler-Benz AG (Mercedes-Benz Group AG)
• Inventors: Kuisl, Max, R.o slashed.sler, Manfred, Strohm, Karl
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/026,693
• Time in Patent Office: 711 Days
• Field of Search: 438/106, 438/110, 438/113, 438/114, 438/343, 438/386, 438/485
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

The invention relates to a semiconductor device which includes a packaged electrical component such as an IC chip, wherein terminal posts are realized within the chip area without additional wafer surface being required beyond the chip edge. A direct feedthrough of the individual electrical connections by way of downwardly extending terminal posts that are connected to bonding pads at the top of the chip results in a small lead length and thus lesser parasitic influences, which in turn results in optimum conditions for use at super-high frequencies. Furthermore, a process for making the semiconductor device offers the option of forming deep vertical trenches on the chip edge and to thus implement separation etching for dicing. During this process, the coverage of the side surface with encapsulating material effects a passivation on the chip edge without further outlay. Expensive rewiring of the connections on the bottom side of the chip is not necessarily due to the terminal posts.

Claims

1. A method for making semiconductor devices, comprising the steps of:

(a) fabricating an array of electrical components at a top side of a substrate, the electrical components including an insulating overcoat layer at the top side, the overcoat layer having holes for electrical connections, the electrical components additionally including bonding pads at the top side;

(b) connecting the electrical components to a cover;

(c) thinning a bottom side of the substrate except for a substrate residue;

(d) etching the substrate residue in a multistage etching process to produce scribe line regions between the electrical components and to produce terminal posts which extend to the bonding pads and which have bottom ends with a predetermined pattern, the terminal posts being insulated from the remainder of the substrate material, the multistage etching process employing a plurality of masking layers and producing steep-sloped sides on the terminal posts;

(e) metallizing the terminal posts; and

(f) dicing the electrical components at the scribe line regions.

2. The method of claim 1, wherein the bonding pads include bonding pads that are located adjacent edges of the electrical components.

3. The methods of claim 1, wherein the bonding pads include bonding pads that are spaced apart from edges of the electrical components.

4. The method of claim 1, wherein the cover employed in step (b) is made of a material selected from the group consisting of silicon, glass, metal, and ceramic material.

5. The method of claim 1, wherein step (b) is conducted by connecting the electrical components to the cover using an adhesive.

6. The method of claim 5, wherein the cover and the adhesive have good thermal conductivity.

7. The method of claim 1, wherein the back side of the substrate is thinned mechanically during step (c) down to a residual thickness in the range of about 75 μ

m to about 200 μ

m.

8. The method of claim 1, wherein the back side of the substrate is thinned chemically during step (c) down to a residual thickness in the range of about 75 μ

m to about 200 μ

m.

9. The method of claim 1, wherein the terminal posts are patterned anisotropically during step (d) using an enhanced rate plasma etching process.

10. The method of claim 1, wherein the multistage etching process of step (d) includes a rate plasma etching process which sculpts the terminal posts and which simultaneously sculpts at least part of each of the scribe line regions.

11. The method of claim 1, wherein step (e) is conducted by sputtering and subsequent electroplating.

12. A method for making semiconductor devices, comprising the steps of:

(a) fabricating an array of electrical components at a top side of a substrate, the electrical components including an insulating overcoat layer at the top side, the overcoat layer having holes for electrical connections, the electrical components additionally including bonding pads at the top side;

(b) connecting the electrical components to a cover;

(c) thinning a bottom side of the substrate except for a substrate residue;

(d) etching the substrate residue in a multistage etching process to produce scribe line regions between the electrical components and to produce terminal posts which extend to the bonding pads and which have bottom ends with a predetermined pattern, the terminal posts being insulated from the remainder of the substrate material, the multistage etching process employing a plurality of masking layers and producing steep-sloped sides on the terminal posts;

(e) coating the entire bottom side of the etched substrate residue with an encapsulating compound;

(f) etching the encapsulating compound off where the terminal posts are located; and

(g) metallizing the terminal posts.

13. The method of claim 12, wherein the bonding pads include bonding pads that are located adjacent edges of the electrical components.

14. The methods of claim 12, wherein the bonding pads include bonding pads that are spaced apart from edges of the electrical components.

15. The method of claim 12, wherein the cover employed in step (b) is made of a material selected from the group consisting of silicon, glass, metal, and ceramic material.

16. The method of claim 12, wherein step (b) is conducted by connecting the electrical components to the cover using an adhesive.

17. The method of claim 16, wherein the cover and the adhesive have good thermal conductivity.

18. The method of claim 12, wherein the back side of the substrate is thinned mechanically during step (c) down to a residual thickness in the range of about 75 μ

m to about 200 μ

m.

19. The method of claim 12, wherein the back side of the substrate is thinned chemically during step (c) down to a residual thickness in the range of about 75 μ

m to about 200 μ

m.

20. The method of claim 12, wherein the terminal posts are patterned anisotropically during step (d) using an enhanced rate plasma etching process.

21. The method of claim 12, wherein the multistage etching process of step (d) includes a rate plasma etching process which sculpts the terminal posts and which simultaneously sculpts at least part of each of the scribe line regions.

22. The method of claim 12, wherein step (e) is conducted by sputtering and subsequent electroplating.

23. The method of claim 12, wherein step (e) is conducted using an encapsulating compound selected from the group consisting of epoxy and PMMA.

24. The method of claim 12, wherein step (f) is conducted in such a manner that the terminal posts stand out after the encapsulating compound has been etched away.

25. The method of claim 12, further comprising the step of forming wiring on the encapsulating compound, the wiring being connected to at least some of the terminal posts.

26. The method of claim 12, further comprising the step of making electrical contact with at least some of the terminal posts using the ball grid array technique.