Stacked devices

• US 6,020,250 A
• Filed: 04/01/1998
• Issued: 02/01/2000
• Est. Priority Date: 08/11/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kenney, Donald McAlpine
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/053,227
• Time in Patent Office: 671 Days
• Field of Search: 438/404, 438/405, 438/408, 438/409, 438/411, 438/421, 438/422, 438/589
• US Class Current: 438/422
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Claims

1. A method of forming a horizontal trench in a substrate, the method comprising the steps of:

providing a bulk single crystal substrate having a p+ diffused layer;

etching a vertical trench in said substrate intersecting said p+ layer,

forming porous silicon in said p+ layer; and

etching away said porous silicon.

2. A method as recited in claim 1 wherein said vertical trench etching step is performed before said p+ doped layer is provided.

3. A method as recited in claim 1, wherein said porous silicon etch is accomplished by first oxidizing said porous silicon to form a silicon oxide and then etching said oxide.