Method of producing a thin layer of semiconductor material

• US 6,020,252 A
• Filed: 05/14/1997
• Issued: 02/01/2000
• Est. Priority Date: 05/15/1996
• Status: Expired due to Term

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Aspar, Bernard, Bruel, Michel, Poumeyrol, Thierry
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US08/856,275
• Time in Patent Office: 993 Days
• Field of Search: 438/458, 438/459, 438/455
• US Class Current: 438/458
• CPC Class Codes: G03F 7/70541 Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate
• CPC Class Codes: Y10T 428/24612 Composite web or sheet

Abstract

A thin layer of semiconductor material is produced by implanting ions through a flat face of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face. The resulting wafer is then subjected to a thermal treatment step in order to achieve coalescence of the microcavities. During or following the thermal treatment, a thin layer is separated from the rest of the wafer by application of mechanical force.

Claims

1. In a method of producing a thin layer of semiconductor material from a wafer of said material, wherein a semiconductor wafer having a flat face is subjected to ion implantation by bombarding said flat face with ions of a rare gas or hydrogen whereby to produce within the volume of said wafer and at a depth approximate to the penetration of the ions, a layer of microcavities separating the wafer into a lower region constituting the mass of the substrate and an upper region constituting the thin film, and the wafer is subjected to a thermal treatment, and the thin film upper region separated from the lower region substrate mass, the improvement wherein the ion implantation step is carried out with an ion dosage level sufficient to create microcavities to embrittle said wafer along a line of implantation, but below the dosage level sufficient to cause the wafer to separate during said thermal treatment, and, during or following said thermal treatment applying a mechanical force sufficient to separate said wafer along the line of implantation into a thin top layer and a lower layer comprising the remainder of the mass of the substrate.

2. A method according to claim 1, and further comprising, between said thermal treatment step and separation step, an intermediate step of treating said wafer so as to produce, at least in part, at least one electronic component in the top layer portion thereof.

3. A method according to claim 2, wherein said intermediate step of treating requiring thermal treatment phases, there are carried out at a temperature below the temperature of said thermal treatment step.

4. A method according to claim 1, and further comprising a step of fixing the flat face side of the wafer to a substrate prior to separating the wafer along the implantation level.

5. A method according to claim 4, wherein said wafer is affixed to a flexible support.

6. A method according to claim 5, wherein said flexible support comprises a sheet of Kapton®

.

7. A method according to claim 4, wherein said semiconductor substrate is affixed to a rigid support.

8. A method according to claim 4, wherein said rigid support comprises a wafer of oxidized silicon.

9. A method according to claim 1, wherein said wafer of semiconductor material comprises monocrystalline silicon.

10. A method according to claim 1, and including the step of covering said wafer of semiconductor material on the flat face side with a layer of non-semiconductor material.

11. A method according to claim 10, wherein said non-semiconductor material comprises a dielectric material.

12. A method according to claim 1, wherein said mechanical force comprises a tensile force.

13. A method according to claim 1, wherein said mechanical force comprises a sheer force.

14. A method according to claim 1, wherein said mechanical force comprises a bending force.

15. A method according to claim 1, wherein said mechanical force comprises one or more mechanical forces selected from the group consisting of a tensile force, a sheer force, a bending force and a mixture of two or more of said forces.