Membrane dielectric isolation IC fabrication

• US 6,020,257 A
• Filed: 01/07/1997
• Issued: 02/01/2000
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/779,679
• Time in Patent Office: 1,120 Days
• Field of Search: 438/626, 438/630
• US Class Current: 438/626
• CPC Class Codes: G03F 7/70483 Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of forming a transistor structure comprising:

providing a flexible membrane having a first dielectric layer and a semiconductor layer;

forming at least a pair of isolation trenches through the semiconductor layer, said isolation trenches filled with dielectric material;

covering the semiconductor layer with a second dielectric layer;

forming a window through the second dielectric layer and semiconductor layer;

etching the semiconductor layer to form a cavity between the first and second dielectric layers and between the pair of isolation trenches; and

forming at least three regions of doped semiconductor material of alternating polarity within the cavity.

2. The method of claim 1 including the additional process step of forming a gate electrode overlying the second dielectric layer.

3. The method of claim 1 including the additional process step of forming an electrical contact to at least one of the three doped regions.

4. The method of claim 3, wherein said electrical contact is formed through the membrane.

5. The method of claim 1, wherein the regions of doped semiconductor material are formed by epitaxial growth.

6. A method of forming a transistor comprising:

providing a flexible membrane of low stress dielectric with a principal surface;

depositing a semiconductor layer on the principal surface of the membrane;

isolating the semiconductor layer in dielectric material;

epitaxially growing three doped regions from the semiconductor layer; and

forming an electrical contact to a first of the three doped regions and forming an electrical contact to a second of the three doped regions.

7. The method of claim 6, including the additional process step of forming a gate electrode overlying the dielectric material.

8. The method of claim 6, including the additional process step of forming a contact to the third of the three doped regions.

9. The method of claim 6, wherein at least one contact is formed through the membrane.

10. The method of claim 8, wherein at least one contact is formed through the membrane.

11. The method of claim 6, wherein the semiconductor layer is epitaxially grown.

12. A method of making a transistor using a membrane having a semiconductor layer interposed between first and second dielectric layers, the method comprising the steps of:

patterning the first dielectric layer so as to expose a portion of the semiconductor layer;

anisotropically etching an opening in the semiconductor layer to a degree that an opening of a desired dimension is formed in the second dielectric layer;

epitaxially growing the semiconductor layer to close the opening thereof; and

forming a first contact in a region of the opening in the second dielectric layer.

13. The method of claim 12 comprising the further step of forming a gate oxide layer within the opening of the second dielectric layer, wherein forming said contact comprises forming a gate electrode overlying said gate oxide layer.

14. The method of claim 13, comprising the further steps of:

etching away the first dielectric layer to expose a planar surface of the semiconductor layer;

performing trench isolation of the transistor; and

forming a third dielectric layer in place of the first dielectric layer.

15. The method of claim 14, comprising the further steps of forming second and third contacts through the third dielectric layer to the semiconductor layer.

16. A method of forming an MOS transistor in which a gate region of the MOS transistor is non-lithographically defined, comprising the steps of:

epitaxially growing semiconductor material having a specified doping within a gate region of the MOSFET such that gate region geometry is controlled by control of the epitaxial growth; and

forming a conductive gate in opposed relation to the gate region.