Method of recovering alignment marks after chemical mechanical polishing of tungsten

• US 6,020,263 A
• Filed: 10/31/1996
• Issued: 02/01/2000
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shih, Tsu, Yu, Chen-Hua
• Primary Examiner(s): CODD, BERNARD P
• Application Number:
  US08/742,229
• Time in Patent Office: 1,188 Days
• Field of Search: 438/691, 438/692, 438/700, 438/704, 438/706, 438/712, 438/723, 216/18, 216/39, 430/314, 430/311, 430/312, 430/313
• US Class Current: 438/692
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention describes a method of forming alignment marks which will be preserved after contact holes in a dielectric have been filled with barrier metal and contact metal and the wafer has been planarized. The alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal. The alignment lines and contact holes are filled with metal at the same time. After the wafer has been planarized, using a method such as chemical mechanical polishing, a small thickness of the dielectric is etched back using vertical dry anisotropic etching which will not remove either the contact metal or barrier metal. This leaves barrier metal and contact metal extending above the plane of the dielectric forming alignment marks. These alignment marks are preserved after subsequent processing steps, such as deposition of a layer of electrode metal.

Claims

1. A method of forming alignment marks, comprising the steps of:

providing a semiconductor wafer having a primary surface;

providing alignment regions within said semiconductor wafer;

providing integrated circuit regions within said semiconductor wafer;

forming a layer of dielectric, having a first thickness, on said primary surface of said semiconductor wafer wherein said layer of dielectric covers said alignment regions of said semiconductor wafer and said layer of dielectric covers said integrated circuit regions of said semiconductor wafer;

forming alignment lines in that part of said layer of dielectric covering said alignment regions of said semiconductor wafer;

forming contact holes in that part of said layer of dielectric covering said integrated circuit regions of said semiconductor wafer;

forming a layer of barrier metal over said semiconductor wafer after forming said alignment lines and said contact holes in said layer of dielectric;

forming a layer of contact metal over said semiconductor wafer after forming said layer of barrier metal over said semiconductor wafer;

removing that part of said layer of barrier metal, that part of said layer of contact metal, and that part of said layer of dielectric which is greater than a first distance above said primary surface of said semiconductor wafer, wherein said first distance is less than said first thickness, thereby leaving said barrier metal and said contact metal only in said alignment lines and said contact holes; and

back etching a second thickness from that part of said layer of dielectric covering said alignment regions of said semiconductor wafer without removing any part of said barrier metal or said contact metal filling said alignment lines, wherein said second thickness is between about 1000 and 1400 Angstroms and is less than said first distance, thereby leaving part of said barrier metal and said contact metal extending said second thickness above said layer of dielectric forming alignment marks.

2. The method of claim 1 wherein said layer of contact metal is tungsten having a thickness of between about 3000 and 8000 Angstroms.

3. The method of claim 1 wherein said layer of barrier metal is titanium/titanium nitride having a thickness of between about 400 and 1000 Angstroms.

4. The method of claim 1 wherein removing that part of said layer of barrier metal, that part of said layer of contact metal, and that part of said layer of dielectric which is greater than a first distance above said primary surface of said semiconductor wafer is accomplished by means of chemical mechanical polishing.

5. The method of claim 1 wherein each of said alignment lines are squares having sides between about 6 and 10 microns long.

6. The method of claim 1 wherein said layer of dielectric is silicon dioxide.

7. The method of claim 1 wherein said first thickness is between about 6500 and 10,500 Angstroms.

8. The method of claim 1 wherein back etching a second thickness from that part of said layer of dielectric covering said alignment regions of said semiconductor wafer is accomplished by means of vertical dry anisotropic etching using CF₄.

9. The method of claim 1 further comprising forming a layer of metal over said semiconductor wafer after forming said alignment marks wherein the top surface of that part of said metal directly over said alignment marks extends a third thickness above the remaining top surface of said layer of metal, thereby forming secondary alignment marks.

10. A method of forming photoresist masks, comprising the steps of:

providing a semiconductor wafer having a primary surface;

providing alignment regions within said semiconductor wafer;

providing integrated circuit regions within said semiconductor wafer;

forming a layer of dielectric, having a first thickness, on said primary surface of said semiconductor wafer wherein said layer of dielectric covers said alignment regions of said semiconductor wafer and said layer of dielectric covers said integrated circuit regions of said semiconductor wafer;

forming alignment lines in that part of said layer of dielectric covering said alignment regions of said semiconductor wafer;

forming contact holes in that part of said layer of dielectric covering said integrated circuit regions of said semiconductor wafer;

forming a layer of barrier metal over said semiconductor wafer after forming said alignment lines and said contact holes in said layer of dielectric;

forming a layer of contact metal over said semiconductor wafer after forming said layer of barrier metal over said semiconductor wafer;

removing that part of said layer of barrier metal, that part of said layer of contact metal, and that part of said layer of dielectric which is greater than a first distance above said primary surface of said semiconductor wafer, wherein said first distance is less than said first thickness, thereby leaving said barrier metal and said contact metal only in said alignment lines and said contact holes;

back etching a second thickness from that part of said layer of dielectric covering said alignment regions of said semiconductor wafer without removing any part of said barrier metal or said contact metal filling said alignment lines, wherein said second thickness is between about 1000 and 1400 Angstroms and is less than said first distance, thereby leaving part of said barrier metal and said contact metal extending said second thickness above said layer of dielectric forming alignment marks;

forming a layer of photoresist on said semiconductor wafer after forming said alignment marks;

providing a projection stepper;

providing a projection mask having a pattern;

exposing said pattern in said layer of photoresist formed on said semiconductor wafer using said projection stepper, said projection mask, and said alignment marks wherein said alignment marks are used to align said pattern to said semiconductor wafer; and

developing said layer of photoresist thereby forming a photoresist mask having said pattern.

11. The method of claim 10 wherein said layer of contact metal is tungsten having a thickness of between about 3000 and 8000 Angstroms.

12. The method of claim 10 wherein said layer of barrier metal is titanium/titanium nitride having a thickness of between about 400 and 1000 Angstroms.

13. The method of claim 10 wherein removing that part of said layer of barrier metal, that part of said layer of contact metal, and that part of said layer of dielectric which is greater than a first distance above said primary surface of said semiconductor wafer is accomplished by means of chemical mechanical polishing.

14. The method of claim 10 wherein each of said alignment lines are squares having sides between about 6 and 10 microns long.

15. The method of claim 10 wherein said layer of dielectric is silicon dioxide.

16. The method of claim 10 wherein said first thickness is between about 6500 and 10,500 Angstroms.

17. The method of claim 10 wherein back etching a second thickness from that part of said layer of dielectric covering said alignment regions of said semiconductor wafer is accomplished by means of vertical dry anisotropic etching using CF₄.

18. The method of claim 10 further comprising forming a layer of metal over said semiconductor wafer after forming said alignment marks wherein the top surface of that part of said metal directly over said alignment marks extends a third thickness above the remaining top surface of said layer of metal, thereby forming secondary alignment marks, wherein said secondary alignment marks are used to align said pattern to said semiconductor wafer.