Wafer test and burn-in platform using ceramic tile supports

• US 6,020,750 A
• Filed: 06/26/1997
• Issued: 02/01/2000
• Est. Priority Date: 06/26/1997
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: LaForce, Mark Raymond, Humenik, James Noel, Berger, Daniel George, Perry, Charles Hampton
• Primary Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US08/882,989
• Time in Patent Office: 950 Days
• Field of Search: 324/754, 324/755, 324/760, 324/765
• US Class Current: 324/756.05
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A plurality of multilayer glass-ceramic substrates are arranged in coplanar relationship in a tile pattern within a support platform. The glass-ceramic substrates and the support platform are both formed of materials having thermal expansion characteristics substantially equal to that of a wafer which is supported by the coplanarly aligned substrates during test and burn-in of the wafer. The present invention effectively solves the problem of providing a single large support member for wafer test and burn-in, which heretofore have been limited in mechanical properties and power capability.

Claims

1. A test head structure for testing a plurality of chips on a wafer having a wafer thermal expansion characteristic, said test head structure comprising:

a support platform formed of a material having a thermal expansion characteristic substantially equal to the wafer thermal expansion characteristic, wherein said support platform has a plurality of openings; and

a plurality of multilayer substrates each formed of a material having a thermal expansion characteristic substantially equal to the wafer thermal expansion characteristic and having a wafer support surface and a back surface, said wafer support surface comprising a plurality of electrical contacts disposed in a pattern, said substrates being mounted on said support platform wherein said back surface of said plurality of multilayer substrates is accessible through said openings.

2. A test head structure, as set forth in claim 1, wherein each of said substrates include a connector contact surface having a plurality of electrical contacts with a connector system, and a plurality of internally disposed electrically conductive circuits providing electrical communication between preselected electrical contacts disposed on the wafer support surface and the connector contact surface of said substrate.

3. A test head structure, as set forth in claim 2, wherein said plurality of openings is for providing electrical contact with the connector contact surface of each of said substrates.

4. A test head structure, as set forth in claim 1, wherein said plurality of multilayer substrates are constructed to apply power and test signals to a plurality of chips on the wafer during a defined test sequence.

5. A test head structure, as set forth in claim 1, wherein said support platform is constructed of an iron-nickel alloy having a thermal coefficient of expansion of about 5.4×

10^-6 m/m/C. (3×

10^-6 in./in./F.).

6. A test head structure, as set forth in claim 1, wherein said multilayer substrates are formed of magnesium aluminosilicate.

7. A test head structure, as set forth in claim 1, wherein said plurality of substrates comprise four equally-sized rectangularly-shaped tiles each having four defined edges, said tiles being arranged on said support platform in a rectangular pattern wherein two edges of each of said tiles are respectively disposed in controlled spaced relationship with a respective edge of two other of said tiles.

8. A test head structure, as set forth in claim 7, wherein each of said substrates includes a connector contact surface having a plurality of electrical contacts with a connector system and said support platform comprises a framework providing support around the edges of each of said multilayer substrates and defines a plurality of openings arranged to expose the plurality of electrical contacts disposed on the connector contact surface of each of the substrates when said substrates are mounted on said support platform.

9. A test head structure, as set forth in claim 1, wherein each of said glass-ceramic substrates has a thickness of from about 1.5 mm (0.06 in.) to about 8 mm (0.3 in.).

10. A test head structure, as set forth in claim 1, wherein:

each of said substrates includes a connector contact surface having a plurality of electrical contacts disposed thereon; and

said support platform includes a first surface having a plurality of electrical contacts arranged for connection with contacts disposed on the connector contact surface of the substrates, a second surface spaced from said first surface and having a plurality of electrical contacts arranged thereon, and a plurality of insulated conductive passageways extending between the electrical contacts disposed on said first surface and the electrical contacts disposed on said second surface of the support platform.

11. A method for forming a test head structure for testing a plurality of chips on a wafer having a predefined thermal expansion characteristic, comprising:

providing a support platform of a material having a thermal expansion characteristic substantially equal to the thermal expansion characteristic of said wafer;

providing a plurality of multilayer substrates, said substrates each having a first planar surface and a second planar surface, said second surface opposite said first surface, said substrates having internally disposed electrical circuits for connecting electrically conductive surface features on said first surface with electrically conductive surface features on said second surface, said substrates being formed of a material having a thermal expansion characteristic substantially equal to the thermal expansion characteristic of said wafer;

forming said electrically conductive surface features on said first surface and on said second surface of each of said substrates;

arranging said substrates in a fixture whereby each of said substrates is arranged in coplanar relationship with other ones of said substrates and at least one defined edge of each of said substrates is disposed in controlled spaced relationship with a respective defined edge of at least one other of said substrates; and

mounting said arranged substrates in said support platform whereby the coplanar relationship of the substrates and the controlled spaced relationship of the respective defined edges of the substrates are maintained in fixed relationship by said support platform during subsequent testing and burn-in processing of the wafer.

12. A method for forming a test head structure, as set forth in claim 11, wherein said method include:

identifying at least two areas on each said substrates for the formation of the defined edges subsequently positioned in controlled spaced relationship with a respective defined edge of another one of said substrates;

machinig a groove in said first surface of each of said substrates, said grooves being respectively aligned with said areas identified for formation of the defined edges;

filling said groove with a composite ceramic-polymer material having a thermal coefficient of expansion no greater than the coefficient of expansion of said substrate material; and

sawing each of said substrates along said filled grooves.

13. A method for forming a test head structure, as set forth in claim 12, wherein said composite ceramic-polymer material comprising the material for filling the machined grooves in the substrates is beta eucryptite in a thermally stable polymer matrix having a thermal coefficient of expansion within at least 3.6×

10^-6 m/m/C(2×

10^-6 in./in./F) of the thermal coefficient of expansion of said wafer.

14. A method for forming a test head structure, as set forth in claim 11, wherein prior to forming electrically conductive surface features on a first surface of each of the substrates, said method includes:

lapping said first surface of each of the substrates; and

polishing said first surface of each of the substrates.

15. A method for forming a test head structure, as set forth in claim 11, wherein said method includes forming electrically conuctive surface features on a second surface of each of the substrates.

16. A method for forming a test head structure, as set forth in claim 11, wherein said method includes depositing a passivation coating on each of said substrates subsequent to forming electrically conductive surface features and prior to arranging the substrates in said fixture.

17. A method for forming a test head structure, as set forth in claim 11, wherein said support platform is constructed of a iron-nickel alloy having a thermal coefficient of expansion of about 5.4×

10^-6 m/m/C(3×

10^-6 in./in./F).

18. A method for forming a test head structure, as set forth in claim 11, wherein said multilayer substrates are formed of magnesium aluminosilicate.