CMOS low-voltage comparator

• US 6,020,768 A
• Filed: 05/13/1998
• Issued: 02/01/2000
• Est. Priority Date: 05/13/1998
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Oak Technology Inc (Qualcomm, Inc.)
• Inventors: Lim, Peter J.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/078,404
• Time in Patent Office: 629 Days
• Field of Search: 327/77, 327/88, 327/89, 327/65, 327/66, 330/257, 323/315, 323/316
• US Class Current: 327/77
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A comparator circuit providing for improved symmetry of operation. The circuit includes two delay paths to facilitate rising and falling input transitions. Such paths are made up of an equal number and type of current mirrors. The circuit also includes an input differential pair wherein both delay paths are coupled to a single transistor of the pair.

Claims

1. A comparator circuit comprising:

a differential input circuit that receives first and second analog input signal transitions for comparison with a reference voltage,

an output circuit that receives charging and discharging current in response to said first and second input signal transitions, respectively;

a first delay path comprising a first plurality of current mirrors coupled to said input circuit and said output circuit that facilitates application of said charging current to said output in response to said first signal transition; and

a second delay path coupled to said input circuit and said output circuit that facilitates application of said discharging current to said output circuit in response to said second signal transition, wherein said first and second delay paths operate in approximately the same amount of time.

2. The comparator circuit of claim 1 wherein said second delay path comprises a second plurality of current mirrors, said first plurality of current mirrors being equal in number to said second plurality of current mirrors.

3. The comparator circuit of claim 2 wherein said first and second plurality of current mirrors each contain an equal number of P-type and N-type current mirrors.

4. The comparator circuit of claim 1 wherein said input circuit comprises a differential pair having a first and a second transistor, and wherein said first and second delay paths are coupled to said first transistor.

5. The comparator circuit of claim 4 wherein said first transistor is coupled to said reference voltage and said second transistor is coupled to an oscillating signal input.

6. A comparator circuit comprising:

a first input transistor coupled to a non-oscillating signal input and a second input transistor coupled to an analog signal;

a first current mirror coupled to said first input transistor and producing a first mirrored current IM1;

a second current mirror coupled to said first input transistor and producing a second mirrored current IM2, said second mirrored current representing a portion of a predetermined current value IMAX; and

an output stage containing a current-sourcing transistor and a current-sinking transistor for producing a digital output, wherein said current-source transistor sources current approximately equal to IM1 and said current-sinking transistor sinks current approximately equal to IMAX-IMA.

7. The comparator circuit of claim 6 wherein

said first current mirror and said current-sourcing transistor delineate a beginning and an end, respectively, of a first delay path;

said second current mirror and said current-sinking transistor delineate a beginning and an end, respectively, of a second delay path; and

said first and second delay paths operate in approximately the same amount of time.

8. The comparator circuit of claim 7 wherein:

said first delay path includes a first plurality of current mirrors;

said second delay path includes a second plurality of current mirrors; and

said first plurality of current mirrors are equal in number to said second plurality of current mirrors.

9. The comparator circuit of claim 8 wherein said first and second plurality of current mirrors each contain an equal number of P-type and N-type current mirrors.

10. A comparator circuit comprising:

an input differential pair containing a first transistor and a second transistor;

a first input path coupled to said first transistor, said first input path receiving an oscillating input signal;

a second input path coupled to said second transistor, said second input path receiving a non-oscillating input signal;

a first delay path coupled to said second transistor that conveys a charging current;

a second delay path coupled to said second transistor that conveys a discharging current; and

an output coupled to said first and second delay paths.

11. The comparator circuit of claim 10 wherein said output receives a net charging current when said oscillating input signal transitions from a first state to a second state.

12. The comparator circuit of claim 11 wherein said output receives a net discharging current when said oscillating input signal transitions from said second state to said first state.

13. The comparator circuit of claim 10 wherein said first and second delay paths comprise a first and second plurality of current mirrors, respectively.

14. The comparator circuit of claim 13 wherein said first plurality of current mirrors are equal in number to said second plurality of current mirrors.

15. The comparator circuit of claim 13 wherein said first and second plurality of current mirrors each contain an equal number of P-type and N-type current mirrors.

16. The comparator circuit of claim 10 wherein said circuit is implemented in CMOS technology.

17. The comparator circuit of claim 10 wherein said second delay path comprises:

a third transistor coupled to said second transistor, said third transistor conducting a first current;

a current source coupled to said third transistor maintaining a maximum current, said maximum current being greater than said first current; and

a fourth transistor coupled to said third transistor and conducting a second current, said first current combined with said second current producing said maximum current.

18. The comparator of claim 17 wherein said first current is a mirrored current.

19. The comparator of claim 18 wherein said second current is approximately equal to said discharging current.