Step-up circuit using two frequencies

• US 6,020,781 A
• Filed: 09/17/1997
• Issued: 02/01/2000
• Est. Priority Date: 12/27/1996
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/932,604
• Time in Patent Office: 867 Days
• Field of Search: 327/534, 327/535, 327/536, 327/537, 327/538, 327/540, 327/541, 327/143, 327/198, 327/291, 327/293, 327/294, 327/276, 327/589, 331/46, 331/48, 331/49, 331/50, 331/57, 331/177 R, 365/189.09, 365/189.11, 365/226, 363/59, 363/60
• US Class Current: 327/541
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/03 Astable circuits

Abstract

A step-up circuit includes a selection control circuit 50 for activating a start/stop signal STP by detecting an external power-supply voltage Vcc, which is stable at 3.3 V, to reach 2.0 V or more, a ring oscillator circuit 30 for generating and outputting a clock of a high frequency Fs when the start/stop signal STP is inactive, a ring oscillator circuit 10 for generating a clock of a low frequency fo, a selection circuit 40 for selecting the output of the oscillator 30 when the start/stop signal STP is inactive and for selecting the output of the oscillator 10 when the start/stop signal is active, and a charging pump circuit 20 driven by the clocks. High frequency Fs is initially used to quickly bring an output voltage up to a desired operating level and low frequency fo is used, in order to conserve power, to maintain the operating level once a predetermined level of the external power supply voltage Vcc has been reached in order to conserve power.

Claims

1. A step-up circuit comprising:

a selection control circuit, receiving an external power supply voltage, for setting a control signal at a first state in response to the external power-supply voltage being lower than a predetermined voltage which is lower than the external power-supply voltage at a stable state;

a clock generating circuit for providing a first clock with a first frequency when said control signal is at said first state and for providing a second clock with a second frequency when said control signal is at a second state, said second frequency being lower than said first frequency; and

a charging pump circuit driven by a selected one of said first and second clocks.

2. A step-up circuit according to claim 1 wherein said clock generating circuit comprises:

a first ring oscillator circuit for generating said first clock when said control signal is at said first state;

a second ring oscillator circuit for generating said second clock; and

a selection circuit for selectively providing said first clock to said charging pump circuit when said control signal is at said first state and for selectively providing said second clock to said charging pump circuit when said control signal is at said first state.

3. A step-up circuit according to claim 1 wherein said clock generating circuit comprises a ring oscillator including an odd number of CMOS inverter stages connected in ring shape, each of said CMOS inverter stages includes:

a CMOS inverter with a pMOS transistor and an nMOS transistor connected in series to each other;

a first pMOS transistor connected between said pMOS transistor of said CMOS inverter and a power-supply potential conductor, its gate electrode receiving a potential to normally turn on said first pMOS transistor;

a second pMOS transistor connected between said pMOS transistor of said CMOS inverter and said power-supply potential conductor, its gate electrode receiving said control signal to turn on said second pMOS transistor when said control signal is at said first state;

a first nMOS transistor connected between said nMOS transistor of said CMOS inverter and a reference potential conductor, its gate electrode receiving a potential to normally turn on said first nMOS transistor; and

a second nMOS transistor connected between said nMOS transistor of said CMOS inverter and said reference potential conductor, its gate electrode receiving a signal associated with said control signal to turn on said second nMOS transistor when said control signal is at said first state.

4. A step-up circuit according to claim 3,

wherein said second pMOS transistor has a value of (gate width)/(gate length) which is larger than that of said first pMOS transistor;

and

wherein said second nMOS transistor has a value of (gate width)/(gate length) which is larger than that of said first nMOS transistor.

5. A step-up circuit according to claim 1 wherein said clock generating circuit comprises:

a first multi-stage inverter circuit including an odd number, which is 5 or more, of inverters connected in cascade;

a second multi-stage inverter circuit including an even number of inverters connected in cascade;

a first switch element connected between an output of a last stage inverter of said first multi-stage inverter circuit and an input of a first stage inverter of said second multi-stage inverter circuit;

a second switch element connected between an output of a last stage inverter of said second multi-stage inverter circuit and an input of a first stage inverter of said first multi-stage inverter circuit; and

a third switch element connected between said output of said last stage inverter of said first multi-stage inverter circuit and said input of said first stage inverter of said first multi-stage inverter circuit;

said first, second and third switch elements being turned on, on and off respectively when said control signal is at said first state, and said first, second and third switch elements being turned off, off and on respectively when said control signal is at said second state.

6. A step-up circuit according to claim 1 wherein said charging pump circuit comprises a capacitor which voltage is added to said external power-supply voltage and which capacitance is switched by said control signal in such a way that a value of said capacitance when said control signal is at said first state is larger than that when said control signal is at said second state.

7. A semiconductor device comprising a step-up circuit formed on a semiconductor chip, wherein said step-up circuit comprises:

a selection control circuit, receiving an external power supply voltage, for setting a control signal at a first state in response to the external power-supply voltage being lower than a predetermined voltage which is lower than the external power-supply voltage at a stable state;

a clock generating circuit for providing a first clock with a first frequency when said control signal is at said first state and for providing a second clock with a second frequency when said control signal is at a second state, said second frequency being lower than said first frequency; and

a charging pump circuit driven by a selected one of said first and second clocks.

8. A semiconductor device according to claim 7, wherein said charging pump circuit is connected with a power supply line having said external power-supply voltage, wherein said semiconductor device further comprises:

a circuit connected with a power supply line having an internal power-supply voltage lower than said external power-supply voltage;

an nMOS step-down transistor, its drain receiving said external power-supply voltage, its source supplying said internal power-supply voltage; and

a control circuit, connected with a power supply line having an output voltage of said charging pump circuit, for providing a constant voltage to a gate electrode of said nMOS step-down transistor.

9. A semiconductor device according to claim 7, wherein said charging pump circuit receives an internal power-supply voltage lower than said external power-supply voltage, wherein said semiconductor device further comprises:

a memory cell including a nMOS transistor with its gate electrode connected to a word line; and

a word driver transistor through which an output voltage of said charging pump circuit is provided to said word line.

10. A boost circuit, in a semiconductor integrated circuit receiving a first power supply voltage and a second power supply voltage, which is lower than the first power supply voltage, to operate, comprising:

a detection circuit connected with a first power supply line having the first power-supply voltage, for detecting when the first power supply voltage is higher than a reference voltage level which is between the first power supply voltage and the second power supply voltage, and for outputting a detection signal;

a clock generating circuit for outputting a clock signal with a frequency, the frequency changing to be lower in response to the detection signal indicating that the first power-supply voltage is higher than the reference voltage; and

a charge pump circuit connected with the first power supply line for outputting a boost voltage in response to the clock signal.