Fast frame buffer system architecture for video display system

• US 6,020,901 A
• Filed: 06/30/1997
• Issued: 02/01/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lavelle, Michael, Koltzoff, Alex, Kehlet, David
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/884,953
• Time in Patent Office: 946 Days
• Field of Search: 345/507-509, 345/213, 345/501, 345/506, 345/502
• US Class Current: 345/545
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for three-dimensional applications. The system includes a frame buffer random access memory system ("FBRAM") that includes video source data and is configurable as a single-buffer or double-buffer, a fast frame buffer controller integrated circuit ("FFB ASIC") that includes system command and video refresh control functions, and a random access memory digital-to-analog converter unit ("RAMDAC") that includes the buffer system timing generator. A FBRAM controller unit provides both parallel accelerated rendering pipeline and direct access paths to the FBRAM unit. The timing generator outputs serial clock and serial clock enable signals, the latter signal preceding horizontal blanking signals by preferably N=1 serial clock pulses to compensate for pixel signal path timing delays.

Claims

1. A frame buffer system for use with a video display system that is useable with a computer system, comprising:

a frame buffer random access memory sub-system (FBRAM) including a source of digital video data, said FBRAM sub-system storing processed said video data to be displayed by said video display system;

a controller unit including a video refresh generator and a command unit coupled to said video refresh generator, coupled to said FBRAM sub-system and to said computer system, said command unit and said video refresh generator providing transfer commands to said FBRAM sub-system including at least one command reflecting state of video refresh required for said video display system; and

a digital-to-analog converter sub-system, coupled to said controller unit and to said FBRAM sub-system, for format-converting said video data for display by said video display system, said digital-to-analog converter sub-system further including a video timing generator that provides timing signals to said frame buffer system.

2. The frame buffer system of claim 1, wherein said video timing generator outputs at least two timing signals selected from a group consisting of (i) a serial clock (SC) signal, (ii) a serial clock enable (SCEN) signal, (iii) a field (FIELD) signal, and (iv) a start each visible horizontal scan line (STSCAN) signal.

3. The frame buffer system of claim 2, wherein said SCEN signal is active during unblanked video time, and is output by said video timing generator in advance of an active horizontal period a number (N) of serial clock cycles constituting a FBRAM pipeline delay for pixels clocking into said digital-to-analog converter sub-system.

4. The frame buffer system of claim 1, wherein said command reflecting state of video refresh includes at least one command selected from a group consisting of (i) a field timing signal (FIELD), (ii) a start each visible horizontal scan line (STSCAN) signal, and (iii) a status (QSF) signal.

5. The frame buffer system of claim 1, wherein said FBRAM sub-system is configurable to at least one configuration selected from a group consisting of (i) a single-buffer sub-system, and a double-buffer sub-system configured into two buffers of pixel data, and one buffer of depth.

6. The frame buffer system of claim 1, wherein said controller unit provides parallel data paths to said FBRAM sub-system that include an accelerated rendering pipeline path and a direct access path.

7. The frame buffer system of claim 6, wherein said controller unit includes a bus interface, coupleable to said computer system, and a pixel data multiplexer, coupled to said bus interface and to said digital-to-analog sub-system;

said parallel data paths being provided between said bus interface and said pixel data multiplexer.

8. The frame buffer system of claim 6, wherein said accelerated rendering pipeline path is provided by a pipeline rendering unit within said controller unit;

said pipeline rendering unit including at least two units selected from the group consisting of (i) a setup unit, (ii) an edge walker unit, and (iii) a span fill unit.

9. A frame buffer system for use with a video display system that is useable with a computer system, comprising:

a frame buffer random access memory sub-system (FBRAM) including a source of digital video data, said FBRAM sub-system storing processed said video data to be displayed by said video display system;

a controller unit, coupled to said FBRAM sub-system and to said computer system so as to provide parallel data paths to said FBRAM sub-system that include an accelerated rendering pipeline path and a direct access path; and

a digital-to-analog converter sub-system, coupled to said controller unit and to said VRAM sub-system, for format-converting said video data for display by said video display system, said digital-to-analog converter sub-system including a video timing generator that provides timing signals to said frame buffer system, said timing signals including at least serial clock pulses and a serial clock enable (SCEN) signal;

wherein said serial clock enable (SCEN) signal is active during unblanked video time and is output by said video timing generator in advance of an active horizontal period a number (N) of serial clock cycles constituting a FBRAM pipeline delay for pixels clocking into said digital-to-analog converter sub-system.

10. The frame buffer system of claim 9, wherein said controller unit includes a pipeline rendering unit provides said accelerated rendering pipeline path;

said pipeline rendering unit including at least two units selected from a group consisting of (i) a setup unit, (ii) an edge walker unit, and (iii) a span fill unit.

11. The frame buffer system of claim 9, wherein said controller unit includes a video refresh generator and a command unit coupled thereto;

said video refresh generator and said command unit providing transfer commands to said FBRAM sub-system including at least one command reflecting state of video refresh required for said video display system.

12. The frame buffer system of claim 9, wherein said FBRAM sub-system is configurable to at least one configuration selected from a group consisting of (i) a single-buffer sub-system, and (ii) a double-buffer sub-system configured into two buffers of pixel data, and one buffer of depth.

13. A method of providing frame buffer video data for use in a video display system useable with a computer system, the method including the following steps:

(a) providing a frame buffer random access memory sub-system (FBRAM) that includes a source of digital video data, said FBRAM sub-system storing processed said video data to be displayed by said video display system;

(b) coupling a controller unit, which controller unit includes a video refresh generator and a command unit coupled thereto, to said FBRAM sub-system and to a said computer system; and

(c) coupling a digital-to-analog converter sub-system to said controller unit and to said FBRAM sub-system for format-converting said video data for display by said video display system, said digital-to-analog converter sub-system including a video timing generator that provides timing signals to said frame buffer system;

(d) causing said command unit and said video refresh generator to provide said FBRAM sub-system with transfer commands that include at least one command reflecting state of video refresh required for said video display system.

14. The method of claim 13, wherein at step (c) said video timing generator outputs at least two timing signals selected from a group consisting of (i) a serial clock (SC) signal, (ii) a serial clock enable (SCEN) signal, (iii) a field (FIELD) signal, and (iv) a start each visible horizontal scan line (STSCAN) signal.

15. The method of claim 14, wherein at step (c), said SCEN signal is active during unblanked video time, and is output by said video timing generator in advance of an active horizontal period a number (N) of serial clock cycles constituting a FBRAM pipeline delay for pixels clocking into said digital-to-analog converter sub-system.

16. The method of claim 13, wherein at step (b) said controller unit is provided with a video refresh generator and a command unit coupled thereto;

wherein said video refresh generator is coupled to said video timing generator to receive therefrom a field timing signal (FIELD) and a start each visible horizontal scan line (STSCAN) signal, and to receive from said FBRAM sub-system a status (QSF) signal;

said command unit and said video refresh generator being coupled to provide transfer commands to said FBRAM sub-system.

17. The method of claim 13, wherein step (a) includes providing said FBRAM sub-system configurable to at least one configuration selected from a group consisting of (i) a single-buffer sub-system, and a double-buffer sub-system configured into two buffers of pixel data, and one buffer of depth.

18. The method claim 13, wherein at step (b), said controller unit provides parallel data paths to said FBRAM sub-system that include an accelerated rendering pipeline path and a direct access path.

19. The method of claim 18, wherein step (b), includes providing a pipeline rendering unit to provide said accelerated rendering pipeline path;

wherein said pipeline rendering unit includes at least two units selected from a group consisting of (i) a setup unit, (ii) an edge walker unit, and (iii) a span fill unit.

20. A method of providing frame buffer system for use with a video display system that is useable with a computer system, the method including the following steps:

(a) providing a frame buffer random access memory sub-system (FBRAM) that includes a source of digital video data, said VRAM sub-system storing processed said video data to be displayed by said video display system;

(b) coupling a controller unit to said FBRAM sub-system and to said computer system so as to provide parallel data paths to said FBRAM sub-system including an accelerated rendering pipeline path and a direct access path;

said controller unit including a video refresh generator and a command unit coupled thereto;

wherein said video refresh generator and said command unit provide transfer commands to said FBRAM sub-system that include at least one command reflecting state of video refresh required for said video display system; and

(c) coupling a digital-to-analog converter sub-system to said controller unit and to said VRAM sub-system, for format-converting said video data for display by said video display system, said digital-to-analog converter sub-system including a video timing generator that provides timing signals to said frame buffer system, said timing signals including at least serial clock pulses and a serial clock enable (SCEN) signal.

21. The method of claim 20, wherein:

said command reflecting state of video refresh includes at least one command selected from a group consisting of (i) a field timing signal (FIELD), (ii) a start each visible horizontal scan line (STSCAN) signal, and (iii) a status (QSF) signal.

22. The method of claim 20, wherein:

at step (c), said serial clock enable (SCEN) signal is active during unblanked video time and is output by said video timing generator in advance of an active horizontal period a number (N) of serial clock cycles constituting a FBRAM pipeline delay for pixels clocking into said digital-to-analog converter sub-system.

23. The method of claim 20, wherein:

at step (b) said controller unit includes a pipeline rendering unit providing said accelerated rendering pipeline path;

said pipeline rendering unit including at least two units selected from a group consisting of (i) a setup unit, (ii) an edge walker unit, and (iii) a span fill unit.