Circuit of sensing a fuse cell in a flash memory
First Claim
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1. A circuit of sensing a fuse cell in a flash memory, comprising:
- a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory;
a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell;
a voltage divider circuit to output the voltage for sensing said fuse cell in said reference circuit according to an output signal of said reference circuit; and
a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit.
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Abstract
This invention discloses a circuit of sensing a fuse cell used for repairing a failed memory cell, the circuit comprising a power-on reset circuit to generate reset pulses at the time of power-on of the flash memory, a reference circuit to latch an initial state according to output signal of the power-on reset circuit, a voltage divider circuit to output the voltage for sensing a fuse cell in said reference circuit according to output signal of the reference circuit, and a main memory cell data latch circuit to latch information on the fuse cell according to output signals of the power-on reset circuit and the reference circuit.
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9 Claims
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1. A circuit of sensing a fuse cell in a flash memory, comprising:
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a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory; a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell; a voltage divider circuit to output the voltage for sensing said fuse cell in said reference circuit according to an output signal of said reference circuit; and a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit. - View Dependent Claims (2, 3, 4, 5)
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6. A circuit of sensing a fuse cell in a flash memory, comprising:
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a power-on resist circuit to generate a reset pulse at the time of power-on of the flash memory; a reference circuit to latch an initial state according to an output signal of said power-on reset circuit, said reference circuit comprising said fuse cell, a sensing circuit to sense data on said fuse cell, a latch circuit to latch data of said fuse cell which are sensed by said sensing circuit, an initializing circuit to initialize said latch circuit according to said output signal of said power-on reset circuit and a delay circuit to delay an output of said latch circuit and to control said fuse cell and said voltage divider circuit; a voltage divider circuit to output the voltage for sensing a fuse cell in said reference circuit according to an output signal of said reference circuit; and a main memory cell data latch circuit to latch information on said fuse cell according to said output signals of said power-on reset circuit and said reference circuit. - View Dependent Claims (7, 8, 9)
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Specification