Direct access to random redundant logic gates by using multiple short addresses

• US 6,021,074 A
• Filed: 09/04/1998
• Issued: 02/01/2000
• Est. Priority Date: 09/04/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Blish, Richard C. II
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/148,684
• Time in Patent Office: 515 Days
• Field of Search: 365/200, 365/201, 365/189.02, 365/230.02
• US Class Current: 365/200
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present invention provides a method for accessing a plurality of gates in a random logic structure. The method includes the steps of providing a first address for a first line coupled to a gate, providing a second address for a second line coupled to the gate, providing at least one additional address for at least one additional line coupled to the gate, and accessing the gate at the intersection of the first, second, and additional addresses. A method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods has been disclosed. The method of the present invention provides a three or more dimensional (segmented) address for each gate which allows for the status of more gates to be specifically ascertained. This allows for more ease in testing, saving valuable time. The method of the present invention also has the added advantage of allowing repair of defective gates with redundant gates.

Claims

1. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:

(a) providing a first address for a first line coupled to a gate;

(b) providing a second address for a second line coupled to the gate;

(c) providing at least one additional address for at least one additional line coupled to the gate; and

(d) accessing the gate at the intersection of the first, second, and the at least one additional address.

2. The method of claim 1, wherein the first address is a row address for a bit line.

3. The method of claim 1, wherein the second address is a column address for a word line.

4. The method of claim 1, wherein the additional address comprises a block address for a block line.

5. The method of claim 4, wherein the additional address further comprises a sub-block address for a sub-block line.

6. A system for accessing a plurality of gates in a random logic structure, comprising:

means for providing a first address for a first line coupled to a gate;

means for providing a second address for a second line coupled to the gate;

means for providing at least one additional address for at least one additional line coupled to the gate; and

means for accessing the gate at the intersection of the first, second, and the least one additional address.

7. The system of claim 6, wherein the first address is a row address for a bit line.

8. The system of claim 6, wherein the second address is a column address for a word line.

9. The system of claim 6, wherein the additional address comprises a block address for a block line.

10. The system of claim 9, wherein the additional address further comprises a sub-block address for a sub-block line.

11. A random logic structure, the structure including a plurality of gates, comprising:

(a) a first line with a first address coupled to a gate;

(b) a second line with a second address coupled to the gate; and

(c) at least one additional line with at least one additional address coupled to the gate, wherein the gate can be accessed at the intersection of the first, second, and the at least one additional address.

12. The random logic structure of claim 11, wherein the first line is a bit line with a row address.

13. The random logic structure of claim 11, wherein the second line is a word line with a column address.

14. The random logic structure of claim 11, wherein the additional line comprises a block line with a block address.

15. The random logic structure of claim 11, wherein the additional line further comprises a sub-block line with a sub-block address.

16. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:

(a) providing a row address for a bit line coupled to a gate;

(b) providing a column address for a word line coupled to the gate;

(c) providing a block address for a block line coupled to the gate; and

(d) accessing the gate at the intersection of the row, column, and block addresses.

17. The method of claim 16, wherein the block line is at a 45 degree orientation in relation to the bit and word lines.

18. A system for accessing a plurality of gates in a random logic structure, comprising:

means for providing a row address for a bit line coupled to a gate;

means for providing a column address for a word line coupled to the gate;

means for providing a block address for a block line coupled to the gate; and

means for accessing the gate at the intersection of the row, column, and block addresses.

19. The system of claim 18, wherein the block line is at a 45 degree orientation in relation to the bit and the word lines.

20. A random logic structure, the structure including a plurality of gates, comprising:

a bit line with a row address coupled to a gate;

a word line with a column address coupled to the gate; and

a block line with a block address coupled to the gate, wherein the gate can be accessed at the intersection of the row, column, and block addresses.

21. The random logic structure of claim 20, wherein the block line is at a 45 degree orientation in relation to the bit and word lines.

22. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:

(a) providing a row address for a bit line coupled to a gate;

(b) providing a column address for a word line coupled to the gate;

(c) providing a block address for a block line coupled to the gate;

(d) providing a sub-block address for a sub-block line coupled to the gate; and

(d) accessing the gate at the intersection of the row, column, block, and sub-block addresses.

23. The method of claim 22, wherein the block line is at a 45 degree orientation in relation to the bit and word lines.

24. The method of claim 22, wherein the sub-block line is at a 135 degree orientation in relation to the bit and word lines.

25. A system for accessing a plurality of gates in a random logic structure, comprising:

means for providing a row address for a bit line coupled to a gate;

means for providing a column address for a word line coupled to the gate;

means for providing a block address for a block line coupled to the gate;

means for providing a sub-block address for a sub-block line coupled to the gate; and

means for accessing the gate at the intersection of the row, column, block, and sub-block addresses.

26. The system of claim 25, wherein the block line is at a 45 degree orientation in relation to the bit and word lines.

27. The method of claim 25, wherein the sub-block line is at a 135 degree orientation in relation to the bit and word lines.

28. A random logic structure, the structure including a plurality of gates, comprising:

(a) a bit line with a bit address coupled to a gate;

(b) a word line with a column address coupled to the gate;

(c) a block line with a block address coupled to the gate; and

(d) a sub-block line with a sub-block address coupled to the gate, wherein the gate can be accessed at the intersection of the bit, column, block, and sub-block addresses.

29. The random logic structure of claim 28, wherein the block line is at a 45 degree orientation in relation to the bit and word lines.

30. The random logic structure of claim 28, wherein the sub-block line is at a 135 degree orientation in relation to the bit and word lines.