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Direct access to random redundant logic gates by using multiple short addresses

  • US 6,021,074 A
  • Filed: 09/04/1998
  • Issued: 02/01/2000
  • Est. Priority Date: 09/04/1998
  • Status: Expired due to Fees
First Claim
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1. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:

  • (a) providing a first address for a first line coupled to a gate;

    (b) providing a second address for a second line coupled to the gate;

    (c) providing at least one additional address for at least one additional line coupled to the gate; and

    (d) accessing the gate at the intersection of the first, second, and the at least one additional address.

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