Direct access to random redundant logic gates by using multiple short addresses
First Claim
1. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:
- (a) providing a first address for a first line coupled to a gate;
(b) providing a second address for a second line coupled to the gate;
(c) providing at least one additional address for at least one additional line coupled to the gate; and
(d) accessing the gate at the intersection of the first, second, and the at least one additional address.
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Accused Products
Abstract
The present invention provides a method for accessing a plurality of gates in a random logic structure. The method includes the steps of providing a first address for a first line coupled to a gate, providing a second address for a second line coupled to the gate, providing at least one additional address for at least one additional line coupled to the gate, and accessing the gate at the intersection of the first, second, and additional addresses. A method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods has been disclosed. The method of the present invention provides a three or more dimensional (segmented) address for each gate which allows for the status of more gates to be specifically ascertained. This allows for more ease in testing, saving valuable time. The method of the present invention also has the added advantage of allowing repair of defective gates with redundant gates.
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Citations
30 Claims
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1. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:
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(a) providing a first address for a first line coupled to a gate; (b) providing a second address for a second line coupled to the gate; (c) providing at least one additional address for at least one additional line coupled to the gate; and (d) accessing the gate at the intersection of the first, second, and the at least one additional address. - View Dependent Claims (2, 3, 4, 5)
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6. A system for accessing a plurality of gates in a random logic structure, comprising:
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means for providing a first address for a first line coupled to a gate; means for providing a second address for a second line coupled to the gate; means for providing at least one additional address for at least one additional line coupled to the gate; and means for accessing the gate at the intersection of the first, second, and the least one additional address. - View Dependent Claims (7, 8, 9, 10)
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11. A random logic structure, the structure including a plurality of gates, comprising:
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(a) a first line with a first address coupled to a gate; (b) a second line with a second address coupled to the gate; and (c) at least one additional line with at least one additional address coupled to the gate, wherein the gate can be accessed at the intersection of the first, second, and the at least one additional address. - View Dependent Claims (12, 13, 14, 15)
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16. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:
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(a) providing a row address for a bit line coupled to a gate; (b) providing a column address for a word line coupled to the gate; (c) providing a block address for a block line coupled to the gate; and (d) accessing the gate at the intersection of the row, column, and block addresses. - View Dependent Claims (17)
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18. A system for accessing a plurality of gates in a random logic structure, comprising:
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means for providing a row address for a bit line coupled to a gate; means for providing a column address for a word line coupled to the gate; means for providing a block address for a block line coupled to the gate; and means for accessing the gate at the intersection of the row, column, and block addresses. - View Dependent Claims (19)
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20. A random logic structure, the structure including a plurality of gates, comprising:
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a bit line with a row address coupled to a gate; a word line with a column address coupled to the gate; and a block line with a block address coupled to the gate, wherein the gate can be accessed at the intersection of the row, column, and block addresses. - View Dependent Claims (21)
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22. A method for accessing a plurality of gates in a random logic structure, comprising the steps of:
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(a) providing a row address for a bit line coupled to a gate; (b) providing a column address for a word line coupled to the gate; (c) providing a block address for a block line coupled to the gate; (d) providing a sub-block address for a sub-block line coupled to the gate; and (d) accessing the gate at the intersection of the row, column, block, and sub-block addresses. - View Dependent Claims (23, 24)
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25. A system for accessing a plurality of gates in a random logic structure, comprising:
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means for providing a row address for a bit line coupled to a gate; means for providing a column address for a word line coupled to the gate; means for providing a block address for a block line coupled to the gate; means for providing a sub-block address for a sub-block line coupled to the gate; and means for accessing the gate at the intersection of the row, column, block, and sub-block addresses. - View Dependent Claims (26, 27)
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28. A random logic structure, the structure including a plurality of gates, comprising:
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(a) a bit line with a bit address coupled to a gate; (b) a word line with a column address coupled to the gate; (c) a block line with a block address coupled to the gate; and (d) a sub-block line with a sub-block address coupled to the gate, wherein the gate can be accessed at the intersection of the bit, column, block, and sub-block addresses. - View Dependent Claims (29, 30)
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Specification