Fast, low cost method of developing code for contact programmable ROMs

• US 6,021,079 A
• Filed: 05/13/1998
• Issued: 02/01/2000
• Est. Priority Date: 05/13/1998
• Status: Expired due to Fees

• Current Assignee: Richard Mann
• Original Assignee: Richard Mann
• Inventors: Worley, Eugene Robert
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/076,989
• Time in Patent Office: 629 Days
• Field of Search: 365/225.7, 365/189.11, 365/230.06
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

Methods are disclosed to make an anti-fuse PROM which can be embedded into a conventional CMOS process with few additional processing steps and a small additional area for the write circuitry. Nominal, low voltage transistors are used to program the PROM such that these transistor remain functional some time after programming for the purposes of verifying functionality of the memory'"'"'s programming code. Once the program code has been verified a low cost production version of the part can be instantly made using standard ROM mask programming.

Claims

1. A PROM memory integrated circuit system comprising

a plurality of ROM cell MOSFET transistors which are arrayed,

a plurality of source lines connected to the sources of said plurality of ROM cell transistors,

a plurality of word lines connected to the gates of said plurality of ROM cell transistors,

a plurality of bit lines placed perpendicular to said plurality of word lines,

anti-fuse insulators placed between the drains of the plurality of said ROM cell transistors and the plurality of said bit lines,

a plurality of row decoder drivers whose output is connected to the plurality of said word lines,

a plurality of row decoders whose outputs connect to the inputs of said plurality of row decoder drivers,

a plurality of column select devices whose output connect to the plurality of said bit lines,

an Input/Output line connecting to the inputs of said plurality of column select devices,

a plurality of column decoders whose outputs control the plurality of said column select devices,

a write driver connected to said Input/Output line, and

a read sense amplifier connected to said Input/Output line.

2. The memory system of claim 1 in which the high voltage supplied to said PROM cell is kept within time-voltage limits so that nominal low voltage transistors can be used to apply the high programmning voltages to said cell while maintaining reliable read operations after programming at the normal operating voltage.

3. The memory system of claim 1 which is reliably read over long periods of time without unintentional programming by keeping the bit line voltage during reading to a value well below the programming bit line voltage or the voltage needed to rupture the anti-fuse insulator.

4. The memory system of claim 1 in which the insulator is removed and a contact or via programming mask with a ROM program code is substituted for low cost production purposes and whose code was developed using the PROM version of said chip.

5. The memory system of claim 1 in which the exposure of circuits to high voltage is minimized by using logic level shifting means at the immediate interface to the PROM cell array.

6. The logic level shift means of claim 5 in which level shifting is performed by conventional CMOS logic gates wherein gates directly interfacing to the PROM array are powered by a programnming voltage supply and all other gates are powered with a supply which has a lower operating voltage.

7. The logic level shift means of claim 5 in which a conventional level shift circuit such as a latch is used.

8. The logic shifting means of claim 5 in which cascode transistors are used to improve reliability and high voltage performance.

9. The logic shifting circuit of claim 8 in which cascode transistors are shorted or removed in the metal mask ROM version in order to improve speed performance.

10. The memory system of claim 1 having a separate pad means for the programmning voltage and a separate pad means for the lower operating voltage of the circuits which do not directly interface to the array and having both pad means with separate interconnect lines such that the mask programming layer of either contacts or vias can be used to connect both pad means together for the mask ROM version.

11. The pad means of claim 10 in which two or more pads that are normally used for the Vdd power of the circuit containing the PROM wherein one pad is used to supply the programming voltage and the others are used to supply the lower operating voltage.

12. The pad means of claim 10 in which there is only on Vdd power pad of said chip and in which a second pad of said chip is introduced at a convenient location which is used as the pad for bringing in the high programming voltage and which is not bonded out for the mask ROM version of the chip but is connected to the Vdd bus via the aforementioned mask programming layer of the mask ROM version of said chip.