Vortex serial communications

• US 6,021,162 A
• Filed: 10/01/1997
• Issued: 02/01/2000
• Est. Priority Date: 10/01/1997
• Status: Expired due to Term

• Current Assignee: Micro Motion Incorporated (Emerson Electric Company)
• Original Assignee: Rosemount Incorporated (Emerson Electric Company)
• Inventors: Feng, Xiaoxin, Gaboury, Michael
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): JIANG, LENNY R
• Application Number:
  US08/941,949
• Time in Patent Office: 853 Days
• Field of Search: 375/242, 375/240, 375/241, 375/238, 702/57, 702/176
• US Class Current: 375/242
• CPC Class Codes: H04L 27/1563 using transition or level detection

Abstract

A method of and apparatus for decoding an encoded signal are disclosed. A first bit of the encoded signal is received and integrated with a super linear integrator to provide a first integration signal. A first reference signal is provided as a function of a previous integration signal associated with a previous bit of the encoded signal by multiplying the previous integration signal by an amount greater than one if the previous bit has a first value, and by multiplying the previous integration signal by an amount less than one if the previous bit has a second value. The first integration signal is compared to the first reference signal and a first bit of an output signal is provided based upon the comparison. The first bit of the output signal is indicative of information encoded in the first bit of the encoded signal.

Claims

1. A decoding circuit for decoding a frequency encoded signal into at least two data states, the circuit comprising:

a super linear integrator which integrates the signal over one-half of a period of the signal to provide an integrated value at the end of the half period, wherein the super linear integrator has a response as a function of time (t) of y=mt^x, where x is a number having a value greater than one and m is a constant;

a reference value generator; and

a comparator coupled to the integrator and to the reference value generator, the comparator comparing the integreated value to the reference value during the other half of the period and providing in response an output indicative of the data state.

2. The decoding circuit of claim 1, wherein the reference value generator comprises a multiplier coupled to the integrator and selectively controlled by a switch, the multiplier generating a reference value by selectively multiplying a preceding integrated value by a factor either greater than or less than one as a function of a preceding data state associated with the preceding integrated value.

3. The decoding circuit of claim 2, wherein the integrator comprises a transconductance amplifier which provides the integrated value at a transconductance amplifier output.

4. The decoding circuit of claim 3, further comprising a track and hold device coupled between the output of the transconductance amplifier and the comparator and between the output of the transconductance amplifier and the multiplier, the track and hold device receiving the integrated value and maintaining the integrated value during the other half of the period.

5. The decoding circuit of claim 4, further comprising a current delay cell coupled between the track and hold device and the multiplier, the current delay cell receiving and storing the integrated value during the other half of the period and providing to the multiplier the preceding integrated value during the other half of the period.

6. The decoding circuit of claim 5, wherein the integrator, the transconductance amplifier, the track and hold device, the current delay cell and the comparator are MOS devices.

7. The decoding circuit of claim 2, wherein the switch is controlled such that the multiplier selectively multiplies the preceding integrated value by a factor of either approximately 1.5 or approximately 0.75 as a function of the preceding data state associated with the preceding integrated value.

8. The decoding circuit of claim 2, wherein the preceding integrated value is equal to one of a maximum integrated value or a minimum integrated value, wherein the factor greater than one and the factor less than one are selected such that the factor greater than one multiplied by the minimum integrated value is approximately equal to the factor less than one multiplied by the maximum integrated value.

9. A process control instrument comprising:

sensor circuitry positioned in a first housing;

measurement circuitry positioned in a second housing and coupled to a process control loop, the measurement circuitry transmitting data related to a process over the process control loop; and

a transmission line including an isolation barrier and carrying an encoded signal between the sensor circuitry and the measurement circuitry, wherein a cycle of the encoded signal having a first period is indicative of a first data state bit, and a cycle of the encoded signal having a second period different than the first period is indicative of a second data state bit;

wherein the sensor circuitry further includes decoding circuitry, the decoding circuitry comprising;

transition detecting circuitry coupled to the transmission line detecting a first transition of the encoded signal during a first cycle and responsively generating a detection signal which increases or decreases from an initial detection signal value, and detecting a second transition of the encoded signal during the first cycle which follows the first transition of the encoded signal during the first cycle, wherein upon detection of the second transition the transition detecting circuitry causes the detection signal to reach a final detection signal value;

comparison circuitry coupled to the transition detecting circuit which compares the final detection signal value to a threshold value at a time subsequent to detection of the second transition; and

output circuitry coupled to the comparison circuitry providing a first data bit having a first type if the final detection signal value is greater than the threshold value, and providing the first data bit having a second type if the final detection signal value is less than the threshold value.

10. The process control instrument of claim 9, wherein the encoded signal is a fifty percent duty cycle signal during both cycles having the first period and cycles having the second period.

11. The process control instrument of claim 10, wherein one of the first and second periods is substantially double the other of the first and second periods.

12. The process control instrument of claim 10, wherein the transition detecting circuitry comprises integration circuitry which receives the encoded signal as an input and which integrates the encoded signal during one half of individual cycles of the encoded signal and provides in response an integration output signal indicative of the period of the encoded signal during the individual cycles of the encoded signal.

13. The process control instrument of claim 12, wherein the integration circuitry includes super linear integration circuitry which provides the integration output signal as a function of time (t) using the relationship y=mt^x, where x is a number having a value greater than one and m is a constant.

14. The process control instrument of claim 12, wherein the integration circuitry provides the integration output signal in the form of a current signal, wherein the threshold value is a threshold current value, and wherein the comparison circuitry includes a current comparator circuit for comparing the integration output signal to the threshold current value.

15. A process control instrument comprising:

sensor circuitry;

measurement circuitry coupled to a process control loop, the measurement circuitry transmitting and receiving data over the process control loop and receiving power from the process control loop;

a barrier coupled between the sensor circuitry and the measurement circuitry and electrically isolating the sensor circuitry from the measurement circuitry;

wherein one of the sensor circuitry and the measurement circuitry further comprises encoding circuitry coupled to the barrier, wherein the encoding circuitry encodes data in a fifty percent duty cycle signal transmitted across the barrier, wherein a cycle of the fifty percent duty cycle signal having a first period is indicative of transmission of a first data state bit, and wherein a cycle of the fifty percent duty cycle signal having a second period different than the first period is indicative of transmission of a second data state bit; and

wherein the other of the sensor circuitry and the measurement circuitry includes decoding circuitry coupled to the barrier, the decoding circuitry receiving the fifty percent duty cycle signal across the barrier and extracting the data from the fifty percent duty cycle signal.

16. The process control instrument of claim 15, wherein one of the first and second periods is substantially double the other of the first and second periods.

17. The process control instrument of claim 15, wherein the decoding circuitry comprises:

integration circuitry which receives the fifty percent duty cycle signal as an input and which integrates the fifty percent duty cycle signal during individual cycles of the fifty percent duty cycle signal and provides in response an integration output signal indicative of the period of the fifty percent duty cycle signal during the individual cycles of the fifty percent duty cycle signal;

reference signal generation circuitry generating a reference signal; and

comparator circuitry which receives the integration output signal and the reference signal as inputs and provides a comparator output signal in response, wherein the comparator output signal associated with each cycle of the fifty percent duty cycle signal is indicative of the data state represented by the cycle of the fifty percent duty cycle signal.

18. The process control instrument of claim 17, wherein the integration circuitry includes super-linear integration circuitry which provides the integration output signal as a super-linear function of the fifty percent duty cycle signal.

19. The process control instrument of claim 17, wherein the integration circuitry provides the integration output signal in the form of a current signal, wherein the reference signal generation circuitry generates the reference signal in the form of a current signal, and wherein the comparator circuitry includes current comparator circuitry.

20. The process control instrument of claim 15, wherein the barrier includes a transformer.

21. A method of decoding an encoded signal, the method comprising:

receiving a first bit of the encoded signal;

integrating the first bit of the encoded signal with a super linear integrator to provide a first integration signal associated with the first bit of the encoded signal;

providing a first reference signal as a function of a previous value of the first integration signal associated with the previous bit of the encoded signal by multiplying the previous value of the first integration signal by an amount greater than one if the previous bit had a first value, and by multiplying the previous value of the first integration signal by an amount less than one if the previous bit had a second value; and

comparing the first integration signal to the first reference signal and providing a first bit of an output signal based upon the comparison, wherein the first bit of the output signal is indicative of information encoded in the first bit of the encoded signal.