Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

• US 6,021,172 A
• Filed: 12/05/1995
• Issued: 02/01/2000
• Est. Priority Date: 01/28/1994
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fossum, Eric R., Pain, Bedabrata, Zhou, Zhimin, Nixon, Robert H., Mendis, Sunetra K.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/567,469
• Time in Patent Office: 1,519 Days
• Field of Search: 257/239, 257/292, 257/294, 257/369, 257/371, 377/60, 327/91, 327/94, 327/278, 327/638
• US Class Current: 377/60
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Claims

1. An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells in said substrate, each of said cells comprising:

a photogate overlying said substrate for accumulating photo-generated charge in an underlying portion of said substrate;

a readout circuit comprising at least an output transistor formed in said substrate;

a charge coupled device section formed on said substrate adjacent said photogate having a sensing node connected to said output transistor and at least one charge coupled device stage for transferring charge from said underlying portion of said substrate to said sensing node; and

said imaging device further comprising an analog-to-digital converter formed in said substrate and connected to said readout circuit; and

wherein said readout circuit is a metal oxide semiconductor circuit formed on said substrate, said substrate being of a first conductivity type, said MOS circuit comprising plural metal oxide field effect transistors of a first conductivity type, a well region of a second conductivity type in said substrate and plural metal oxide semiconductor transistors of a second conductivity type formed in said well region.

2. The imaging device of claim 1 wherein:

said sensing node of said charge coupled device stage comprises a floating node; and

said charge coupled device stage comprises a transfer gate between said floating node and said photogate.

3. The imaging device of claim 2 wherein said floating node is one of:

(a) a floating diffusion, and (b) a floating gate.

4. The imaging device of claim 2 further comprising:

a drain diffusion connected to a drain bias voltage; and

a reset gate between said floating node and said drain diffusion, said reset gate connected to a reset control signal.

5. The imaging device of claim 4 wherein said output transistor comprises a field effect source follower transistor, said floating node being connected to a gate of said source follower transistor.

6. The imaging device of claim 4 wherein said readout circuit further comprises a double correlated sampling circuit comprising:

a pair of sample and hold field effect transistors formed in said substrates, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said source follower transistor;

a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors; and

means for sensing a potential of each of said sample and hold capacitors at respective intervals.

7. The imaging device of claim 6 further comprising means for sensing a difference between the potentials of said pair of sample and hold capacitors.

8. The imaging device of claim 6 further comprising means for shorting across each of said pair of sample and hold capacitors simultaneously while said means for sensing measures a fixed pattern noise difference.

9. The imaging device of claim 6 wherein said focal plane array of cells is organized by rows and columns of said cells, and wherein said means for sensing at period intervals comprises:

a row select field effect transistor formed in said substrate having its source and drain connected between said source of said source follower transistor and said pair of sample and hold transistors and a gate connected to a row select signal;

a pair of sample and hold output transistors having respective gates and sources connected across respective ones of said pair of sample and hold capacitors, and having respective drains;

respective differential output nodes of said correlated double sampling circuit;

a pair of column select transistors formed in said substrate each having a source and drain connected between a drain of a respective one of said sample and hold output transistors and a gate connected to a column select signal.

10. The imaging device of claim 9 wherein each of said transistors is a metal oxide field effect transistor, said source follower transistor, said row select transistor and said pair sample and hold transistors being n-channel devices, said pair of sample and hold output transistors and said pair of column select transistors being p-channel devices.

11. The imaging device of claim 9 wherein said analog-to-digital converter is connected to the readout circuits of all cells in a given one of said column, said imaging device comprising an analog-to-digital converter for each one of said column connected to the readout circuits of the cells in the respective column.

12. The imaging device of claim 11 wherein said analog-to-digital converter comprises one of:

(a) a sigma delta modulation circuit, (b) a single slope analog-to-digital converter, (c) an analog-to-digital converter employing successive approximations.

13. The imaging device of claim 1 further comprising means for periodically resetting a potential of said sensing node to a predetermined potential.

14. The imaging device of claim 1 wherein said readout circuit further comprises a double correlated sampling circuit having an input node connected to said output transistor.

15. The imaging device of claim 1 further comprising a micro-lens layer overlying said substrate, said micro-lens layer comprising:

a refractive layer;

individual lenses formed in said layer in registration with individual ones of said cells, each of said individual lenses having a curvature for focusing light toward a center portion of the respective cell.

16. The imaging device of claim 15 wherein said refractive layer comprises an oxide of silicon.

17. The imaging device of claim 16 wherein said refractive layer comprises polyimide.

18. The imaging device of claim 15 wherein each of said individual lenses covers portions of the corresponding cell including said photogate as well as said charge coupled device stage and said readout circuit.

19. The imaging device of claim 1 wherein said analog-to-digital converter comprises one of:

(a) a sigma delta modulation circuit, b) a single slope analog-to-digital converter, (c) an analog-to-digital converter employing successive approximations.

20. An imaging device comprising:

a monolithic semiconductor integrated circuit substrate;

a focal plane array of pixel cells formed on said integrated circuit substrate, each of said pixel cells comprising;

a photogate overlying said substrate, accumulating photo-generated charge in an underlying portion of said substrate;

a charge transfer section, receiving the accumulated photo-generated charge from the photogate; and

a coupling section, formed on said substrate adjacent said charge transfer section, having a sensing node connected to said photogate through said charge transfer section, wherein said charge transfer section transfers stored charge from said photogate to said sensing node; and

said focal plane array including a plurality of units, each unit of said focal plane array including at least one of said pixel cells, and further comprising;

a readout controller which controls readout of said pixel cells to read out all pixel cells of each unit in parallel; and

at least two analog to digital converters, formed in said substrate, and each connected to one pixel cell of said unit to read out information from said pixel cells of said unit in parallel, wherein said units are rows, said focal plane array is arranged into a plurality of rows and columns, one A/D converter being associated with each column of said array so that said columns of pixel cells are connected to respective A/D converters in parallel relative to one another and an entire row of pixel cells is simultaneously read and A/D converted.

21. A device for imaging capturing and processing, comprising:

(1) a focal plane array of pixel cells, each of said pixel cells including a monolithic semiconductor integrated circuit substrate, wherein each of said pixel cells includes;

(a) a photogate overlying a first portion of said substrate and operating to accumulate photo-generated charge in a first portion of said substrate that underlies said photogate; and

(b) a charge transfer section, formed in said substrate adjacent said photogate, having a sensing node adjacent said photogate and at least one charge coupling stage, operating to transfer charge from said first portion of said substrate to said sensing node;

(2) an A/D converter, formed on said integrated circuit substrate and connected to said sensing node of at least one of said pixel cells, but less than all of said pixel cells, so that less than all of said pixel cells are attached to said A/D converter, wherein said A/D converter includes;

(a) a signal path portion, having an input receiving said signal and an output coupling said signal;

(b) a reference path, selectively providing a full scale signal;

(c) a signal-combining element, receiving said signal on said signal path and said signal on said reference path, and outputting a value indicative of a combination signal thereof;

(d) an integrating element, connected to receive and integrate said combination signal;

(e) a comparing element connected to an output of said integrating element, comparing said combination signal with a reference and producing an output indicative thereof; and

(f) a latch element which counts a ratio of values of said output.

22. A device as in claim 21 wherein said latch element produces a binary signal indicative of a result of the comparison;

and said reference path of said signal-combining element comprises a first branch which adds the full scale signal when the result of the comparison is a first amount, and a second branch which adds another signal when the result is a second amount.

23. A device as in claim 22 wherein said first branch adds the full scale signal and second branch subtracts a full scale signal.

24. A device as in claim 21 wherein said integrator element includes a capacitor therein.

25. A device as in claim 24 wherein said capacitor is an MOS capacitor.

26. A device as in claim 24 further comprising a reset switch across the capacitor, said reset switch resetting a value of the integrator at the beginning of each pixel conversation.

27. A device as in claim 26 wherein said reset switch is an MOS transistor.