Automatic capture and processing of facsimile transmissions

• US 6,021,186 A
• Filed: 11/14/1997
• Issued: 02/01/2000
• Est. Priority Date: 04/17/1995
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Suzuki, Kiyoshi, Hull, Jonathan J., Baxter, Michael A.
• Primary Examiner(s): Chan, Wing F.
• Application Number:
  US08/970,190
• Time in Patent Office: 809 Days
• Field of Search: 379/100.01, 379/100.02, 379/100.03, 379/100.05, 379/100.12-100.17, 379/110.01, 379/93.01, 379/93.05-93.08 , 379/93.14-93.17, 379/93.28-93.34, 379/90.01, 358/400, 358/402, 358/403, 358/406, 358/407, 358/434, 358/442, 358/444, 358/468
• US Class Current: 379/100.12
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 8/47 Retargetable compilers
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading

Abstract

An automatic capture device, situated between a telephone line and a fax machine, provides real-time monitoring, recording, and selective modification of fax transmissions, and forwarding of the fax data to a computer interface. The automatic capture device is dynamically reconfigurable, capable of adaptation to a variety of facsimile formats and computer interfaces.

Claims

1. A facsimile apparatus comprising:

circuitry for sensing and demodulating a facsimile signal on a telephone line; and

a dynamically reconfigurable processor, coupled to the sensing and demodulating circuitry, for receiving and selectively modifying the facsimile signal, the dynamically reconfigurable processor comprising;

a reconfigurable logic unit; and

a memory, coupled to the reconfigurable logic unit, storing;

a plurality of configuration sets, each configuration set specifying a configuration of the reconfigurable logic unit, each configuration defining an instruction set architecture of the dynamically reconfigurable processor; and

a plurality of instructions to be executed by the reconfigurable logic unit in response to a timing signal, at least one instruction comprising a reconfiguration instruction for reconfiguring the reconfigurable logic unit with one of the configuration sets, at least one reconfiguration instruction executed in response to sensing the facsimile signal on the telephone line.

2. The apparatus of claim 1, further comprising:

a communications interface, coupled to the dynamically reconfigurable processor, for transmitting the facsimile signal to a storage unit, wherein at least one instruction set architecture includes instructions optimized for transmitting the facsimile signal to the storage unit.

3. The apparatus of claim 2, further comprising:

a storage unit, coupled to the communications interface, for receiving and storing a representation of the facsimile signal.

4. The apparatus of claim 1, wherein the circuitry for sensing and demodulating the facsimile signal comprises:

a transformer, coupled to the telephone line, having a high impedance for diverting at least a portion of the facsimile signal from the telephone line; and

a codec, coupled to the transformer and the dynamically reconfigurable processor, for demodulating the diverted signal and providing the demodulated signal to the dynamically reconfigurable processor.

5. The apparatus of claim 4, further comprising:

an amplifier, coupled between the transformer and the codec, for amplifying the diverted signal.

6. The apparatus of claim 1, wherein the reconfigurable logic unit is a programmable gate array.

7. The apparatus of claim 1, wherein the memory is a flash-programmable read-only memory device.

8. The apparatus of claim 1, wherein the dynamically reconfigurable processor further comprises:

a page buffer, coupled to the reconfigurable logic unit, for temporarily storing a representation of the facsimile signal received by the dynamically reconfigurable processor.

9. The apparatus of claim 1, wherein the reconfigurable logic unit is adapted to provide at least one instruction set architecture optimized for receiving the facsimile signal and at least one instruction set architecture optimized for selectively modifying the facsimile signal.

10. The apparatus of claim 9, wherein the instruction set architecture optimized for selectively modifying the facsimile signal comprises instructions optimized for encrypting the facsimile signal.

11. The apparatus of claim 9, wherein the instruction set architecture optimized for selectively modifying the facsimile signal comprises instructions optimized for decrypting the facsimile signal.

12. The apparatus of claim 9, wherein the instruction set architecture optimized for selectively modifying the facsimile signal comprises instructions optimized for compressing the facsimile signal.

13. The apparatus of claim 9, wherein the instruction set architecture optimized for selectively modifying the facsimile signal comprises instructions optimized for decompressing the facsimile signal.

14. The apparatus of claim 9, wherein the instruction set architecture optimized for receiving the facsimile signal comprises instructions optimized for controlling the circuitry for sensing and demodulating the facsimile signal.

15. The apparatus of claim 1, further comprising:

circuitry, coupled to the dynamically reconfigurable processor and the telephone line, for modulating and sending a facsimile signal via the telephone line.

16. The apparatus of claim 15, wherein the circuitry for modulating and sending a facsimile signal comprises:

a codec, coupled to the dynamically reconfigurable processor, for modulating a facsimile signal; and

a transformer, coupled to the codec and the telephone line, having a low impedance for receiving the modulated signal from the codec and producing a facsimile signal on the telephone line.

17. The apparatus of claim 1, further comprising:

a ring detector, coupled to the telephone line and the dynamically reconfigurable processor, for detecting a ring signal on the telephone line, wherein the reconfigurable logic unit is reconfigured in response to detecting the ring signal to provide an instruction set architecture optimized for receiving the facsimile signal.

18. The apparatus of claim 1, further comprising:

a load detector, coupled to the telephone line and the dynamically reconfigurable processor, for detecting a line current on the telephone line, wherein the reconfigurable logic unit is reconfigured in response to detecting the line current to provide an instruction set architecture optimized for receiving the facsimile signal.

19. The apparatus of claim 1, wherein the telephone line extends between first and second facsimile machines, the apparatus further comprising:

a switch, coupled to the telephone line and the dynamically reconfigurable processor, for disconnecting the first facsimile machine from the telephone line such that the dynamically reconfigurable processor may intercept a facsimile signal from, or send a facsimile signal to, the second facsimile machine.

20. In a facsimile apparatus for receiving and selectively modifying a facsimile signal on a telephone line, the apparatus comprising a dynamically reconfigurable processor, the dynamically reconfigurable processor comprising a reconfigurable logic unit and a memory, the memory comprising a plurality of configuration sets, each configuration set specifying a configuration of the reconfigurable logic unit, each configuration defining an instruction set architecture, the memory further comprising a plurality of instructions, at least one instruction comprising a reconfiguration instruction for reconfiguring the reconfigurable logic unit with one of the configuration sets, a method for receiving and selectively modifying the facsimile signal comprising:

sensing the facsimile signal on the telephone line;

in response to sensing the facsimile signal, reconfiguring the reconfigurable processing unit to an instruction set architecture optimized for receiving the facsimile signal; and

receiving the facsimile signal.

21. The method of claim 20, wherein the telephone line extends between first and second facsimile machines, the sensing step comprising:

determining which of the first and second facsimile machines is generating the facsimile signal; and

disconnecting from the telephone line the facsimile machine that is not generating the facsimile signal.

22. The method of claim 20, further comprising:

temporarily storing a representation of the facsimile signal in a page buffer.

23. The method of claim 20, further comprising:

determining whether the facsimile signal is encrypted;

in response to the facsimile signal being encrypted, reconfiguring the reconfigurable processing unit to an instruction set architecture optimized for decrypting the facsimile signal; and

decrypting the facsimile signal.

24. The method of claim 20, further comprising:

determining whether the facsimile signal is compressed;

in response to the facsimile being compressed, reconfiguring the reconfigurable processing unit to an instruction set architecture optimized for decompressing the facsimile signal; and

decompressing the facsimile signal.

25. The method of claim 20, further comprising:

detecting a format of the facsimile signal;

reconfiguring the reconfigurable processing unit to an instruction set architecture optimized for receiving the facsimile signal in the detected format; and

receiving the facsimile signal in the detected format.

26. The method of claim 20, further comprising:

in response to receiving the facsimile signal, reconfiguring the reconfigurable processing unit to an instruction set architecture optimized for transmitting the facsimile signal to a storage unit; and

transmnitting the facsimile signal to the storage unit.