Method and apparatus for integrated ciphering and hashing

• US 6,021,201 A
• Filed: 01/07/1997
• Issued: 02/01/2000
• Est. Priority Date: 01/07/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Davis, Derek L., Bakhle, Ashutosh
• Primary Examiner(s): Hayes, Gail O.
• Assistant Examiner(s): SONG, HOSUK
• Application Number:
  US08/779,567
• Time in Patent Office: 1,120 Days
• Field of Search: 380/37, 380/29, 380/25, 380/28, 380/50, 380/30, 709/400
• US Class Current: 713/189
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
• CPC Class Codes: H04L 9/3249 using RSA or related signature schemes, e.g. Rabin scheme

Abstract

A cryptography unit having a cipher unit and a hash unit coupled in parallel for simultaneous ciphering and hashing. The cipher unit implements a cipher algorithm that operates on a data block having a first predetermined size M. The hash unit implements a hash algorithm on a data block having a second predetermined size N. Buffers of a size Q, where Q is an integer multiple of M and N, are employed to receive the input data into the present invention. A security unit that ensures that the cipher unit and the hash unit operate on the same data block of size Q is also provided.

Claims

1. A cryptographic device comprising:

a) a cipher unit to perform a ciphering operation on input data, the cipher operation operating on a data block having a first predetermined size M;

b) a hash unit to perform a hash operation on the input data generally in parallel with the ciphering operation, the hash operation operating on a data block having a second predetermined size N;

c) an input buffer to receive the input data, the buffer having a size Q, the Q being an integer multiple of M and N; and

d) a security enhancement unit coupled to the cipher unit and the hash unit, the security enhancement unit ensuring that both the cipher unit and the hash unit have completed processing a current data block before a next data block is provided to the cipher unit and the hash unit.

2. The cryptographic device of claim 1, wherein the security enhancement unit includes an address generator, coupled to the input buffer, the address generator ensuring that the input buffer, having the current data block, is not overwritten until the cipher unit and the hash unit have both completed processing the current data block.

3. The cryptographic device of claim 2, wherein the security enhancement unit further includes a signal generator, the signal generator having a first input for receiving a first signal indicating that the cipher unit has completed processing the current data block, and a second input for receiving a second signal indicating that the hash unit has completed processing the current data block, the signal generator responsive to the first and second signals selectively generates a DONE signal indicating to an external device that the cryptography unit is ready for the next data block.

4. The cryptographic device of claim 1, wherein the cipher operation operates on a data block having a block size of 64 bits (M=64);

and

wherein the hash operation operates on a data block having a block size of 512 bits (N=512).

5. The cryptographic device of claim 1, wherein the cipher unit performs encryption and decryption on the data block.

6. The cryptographic device of claim 1 further comprising an output buffer coupled to the cipher unit, the hash unit and the security enhancement unit, wherein the ciphering operation is a DES scheme.

7. The cryptographic device of claim 6, further comprising a selector having inputs coupled to both the input buffer and the output buffer and an output coupled to the hash unit.

8. The cryptographic device of claim 1, wherein the input buffer includes a triple parted register random access memory.

9. The cryptographic device of claim 1, wherein the security enhancement unit includes a first input, the input indicating to the security enhancement unit that the slower of the cipher unit and hash unit have completed processing, the security enhancement unit generating a done signal based on the input signal, the security enhancement unit providing the DONE signal to the faster of either the cipher unit or the hash unit.

10. A data processing system comprising:

a) a data source for providing a data block to be ciphered and hashed;

b) an integrated cipher and hash unit, coupled to the data source, having a cipher unit to perform a ciphering operation on the data block and a hash unit to perform a hash operation concurrently on the data block;

wherein the integrated cipher and hash unit includes a security enhancement unit that ensures that both the cipher unit and the hash unit have completed processing a current data block before a next data block is received from the data source.

11. The data processing system of claim 10, wherein the integrated cipher and hash unit further includes an input buffer for receiving the data block, wherein the security enhancement unit includes an address generator, coupled to the buffer, the address generator ensuring that said input buffer having the current data block is not overwritten until the cipher unit and the hash unit have both completed processing the current data block.

12. The data processing system of claim 11, wherein the security enhancement unit further includes a signal generator, the signal generator having a first input for receiving a first signal indicating that the cipher unit has completed processing the current data block, and a second input for receiving a second signal indicating that the cipher unit has completed processing the current data block, the signal generator responsive to the first and second signals selectively generates a DONE signal indicating to an external device that the cryptography unit is ready for the next data block.

13. The data processing system of claim 10, wherein the cipher operation operates on a data block having a block size of 64 bits;

and

wherein the hash operation operates on a data block having a block size of 512 bits.

14. The data processing system of claim 10, wherein the cipher unit performs encryption and decryption on the data block.

15. The data processing system of claim 10, wherein said ciphering operation is a DES scheme.

16. The data processing system of claim 10, wherein the hash operation is one of an MD5 scheme and an SHA scheme.

17. The data processing system of claim 10 further comprising a verification unit coupled to the integrated cipher and hash unit.

18. A cryptographic device comprising:

a cipher unit to perform a ciphering operation on input data;

a hash unit to perform a hash operation on the input data generally in parallel with the ciphering operation so that the ciphering and hash operations are atomic; and

a security enhancement unit coupled to the cipher unit and the hash unit, the security enhancement unit to control the cipher unit and the hash unit.